* [Qemu-devel] [PATCH] target-mips: fix ROTR and DROTR by zero
@ 2010-02-20 18:24 Nathan Froyd
2010-02-23 19:03 ` Aurelien Jarno
0 siblings, 1 reply; 2+ messages in thread
From: Nathan Froyd @ 2010-02-20 18:24 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-mips/translate.c | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index dfea6f6..de5ac18 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1476,6 +1476,8 @@ static void gen_shift_imm(CPUState *env, DisasContext *ctx, uint32_t opc,
tcg_gen_rotri_i32(t1, t1, uimm);
tcg_gen_ext_i32_tl(cpu_gpr[rt], t1);
tcg_temp_free_i32(t1);
+ } else {
+ tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
}
opn = "rotr";
break;
@@ -1495,6 +1497,8 @@ static void gen_shift_imm(CPUState *env, DisasContext *ctx, uint32_t opc,
case OPC_DROTR:
if (uimm != 0) {
tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm);
+ } else {
+ tcg_gen_mov_tl(cpu_gpr[rt], t0);
}
opn = "drotr";
break;
--
1.6.3.2
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [Qemu-devel] [PATCH] target-mips: fix ROTR and DROTR by zero
2010-02-20 18:24 [Qemu-devel] [PATCH] target-mips: fix ROTR and DROTR by zero Nathan Froyd
@ 2010-02-23 19:03 ` Aurelien Jarno
0 siblings, 0 replies; 2+ messages in thread
From: Aurelien Jarno @ 2010-02-23 19:03 UTC (permalink / raw)
To: Nathan Froyd; +Cc: qemu-devel
On Sat, Feb 20, 2010 at 10:24:07AM -0800, Nathan Froyd wrote:
>
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Thanks applied.
> ---
> target-mips/translate.c | 4 ++++
> 1 files changed, 4 insertions(+), 0 deletions(-)
>
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index dfea6f6..de5ac18 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -1476,6 +1476,8 @@ static void gen_shift_imm(CPUState *env, DisasContext *ctx, uint32_t opc,
> tcg_gen_rotri_i32(t1, t1, uimm);
> tcg_gen_ext_i32_tl(cpu_gpr[rt], t1);
> tcg_temp_free_i32(t1);
> + } else {
> + tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
> }
> opn = "rotr";
> break;
> @@ -1495,6 +1497,8 @@ static void gen_shift_imm(CPUState *env, DisasContext *ctx, uint32_t opc,
> case OPC_DROTR:
> if (uimm != 0) {
> tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm);
> + } else {
> + tcg_gen_mov_tl(cpu_gpr[rt], t0);
> }
> opn = "drotr";
> break;
> --
> 1.6.3.2
>
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 2+ messages in thread
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