From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NjbOH-0006o5-BV for qemu-devel@nongnu.org; Mon, 22 Feb 2010 11:44:13 -0500 Received: from [199.232.76.173] (port=58542 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NjbOG-0006nq-WD for qemu-devel@nongnu.org; Mon, 22 Feb 2010 11:44:13 -0500 Received: from Debian-exim by monty-python.gnu.org with spam-scanned (Exim 4.60) (envelope-from ) id 1NjbOF-0002w9-Hj for qemu-devel@nongnu.org; Mon, 22 Feb 2010 11:44:12 -0500 Received: from moutng.kundenserver.de ([212.227.126.187]:60624) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NjbOE-0002vz-RV for qemu-devel@nongnu.org; Mon, 22 Feb 2010 11:44:11 -0500 From: Stefan Weil Date: Mon, 22 Feb 2010 17:43:52 +0100 Message-Id: <1266857032-10078-1-git-send-email-weil@mail.berlios.de> In-Reply-To: <4B82A142.9060608@mail.berlios.de> References: <4B82A142.9060608@mail.berlios.de> Subject: [Qemu-devel] [PATCH] tcg/ppc: Add missing conditional compilation List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: QEMU Developers Cc: blauwirbel@gmail.com, jay.foad@gmail.com, agraf@suse.de INDEX_op_qemu_ld32s is only used when TCG_TARGET_REG_BITS == 64. This fixes a compile error (reported by Alexander Graf). Signed-off-by: Stefan Weil --- tcg/ppc/tcg-target.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c index 903b69f..9f801c2 100644 --- a/tcg/ppc/tcg-target.c +++ b/tcg/ppc/tcg-target.c @@ -1693,7 +1693,9 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_qemu_ld16u, { "r", "L" } }, { INDEX_op_qemu_ld16s, { "r", "L" } }, { INDEX_op_qemu_ld32u, { "r", "L" } }, +#if TCG_TARGET_REG_BITS == 64 { INDEX_op_qemu_ld32s, { "r", "L" } }, +#endif { INDEX_op_qemu_ld64, { "r", "r", "L" } }, { INDEX_op_qemu_st8, { "K", "K" } }, @@ -1706,7 +1708,9 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_qemu_ld16u, { "r", "L", "L" } }, { INDEX_op_qemu_ld16s, { "r", "L", "L" } }, { INDEX_op_qemu_ld32u, { "r", "L", "L" } }, +#if TCG_TARGET_REG_BITS == 64 { INDEX_op_qemu_ld32s, { "r", "L", "L" } }, +#endif { INDEX_op_qemu_ld64, { "r", "L", "L", "L" } }, { INDEX_op_qemu_st8, { "K", "K", "K" } }, -- 1.6.6.1