From: Aurelien Jarno <aurelien@aurel32.net>
To: qemu-devel@nongnu.org
Cc: Andrzej Zaborowski <andrew.zaborowski@intel.com>,
Aurelien Jarno <aurelien@aurel32.net>
Subject: [Qemu-devel] [PATCH] tcg/arm: implement andc op
Date: Thu, 4 Mar 2010 22:54:09 +0100 [thread overview]
Message-ID: <1267739649-27599-1-git-send-email-aurelien@aurel32.net> (raw)
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
tcg/arm/tcg-target.c | 4 ++++
tcg/arm/tcg-target.h | 2 +-
2 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index dabc0f5..756f131 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -1445,6 +1445,9 @@ static inline void tcg_out_op(TCGContext *s, int opc,
case INDEX_op_and_i32:
c = ARITH_AND;
goto gen_arith;
+ case INDEX_op_andc_i32:
+ c = ARITH_BIC;
+ goto gen_arith;
case INDEX_op_or_i32:
c = ARITH_ORR;
goto gen_arith;
@@ -1652,6 +1655,7 @@ static const TCGTargetOpDef arm_op_defs[] = {
{ INDEX_op_div2_i32, { "r", "r", "r", "1", "2" } },
{ INDEX_op_divu2_i32, { "r", "r", "r", "1", "2" } },
{ INDEX_op_and_i32, { "r", "r", "rI" } },
+ { INDEX_op_andc_i32, { "r", "r", "rI" } },
{ INDEX_op_or_i32, { "r", "r", "rI" } },
{ INDEX_op_xor_i32, { "r", "r", "rI" } },
{ INDEX_op_neg_i32, { "r", "r" } },
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index ae2ece6..4cad967 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -65,7 +65,7 @@ enum {
#define TCG_TARGET_HAS_not_i32
#define TCG_TARGET_HAS_neg_i32
// #define TCG_TARGET_HAS_rot_i32
-// #define TCG_TARGET_HAS_andc_i32
+#define TCG_TARGET_HAS_andc_i32
// #define TCG_TARGET_HAS_orc_i32
#define TCG_TARGET_HAS_GUEST_BASE
--
1.7.0
reply other threads:[~2010-03-04 21:54 UTC|newest]
Thread overview: [no followups] expand[flat|nested] mbox.gz Atom feed
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