From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Nwenq-0007Wb-2Z for qemu-devel@nongnu.org; Tue, 30 Mar 2010 13:00:34 -0400 Received: from [140.186.70.92] (port=33423 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Nweno-0007W9-Rg for qemu-devel@nongnu.org; Tue, 30 Mar 2010 13:00:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1Nwenm-0008Q0-Dh for qemu-devel@nongnu.org; Tue, 30 Mar 2010 13:00:32 -0400 Received: from liberdade.minaslivre.org ([72.232.254.139]:33678) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1Nwenm-0008Pa-9l for qemu-devel@nongnu.org; Tue, 30 Mar 2010 13:00:30 -0400 From: Thadeu Lima de Souza Cascardo Date: Tue, 30 Mar 2010 13:58:53 -0300 Message-Id: <1269968333-9464-1-git-send-email-cascardo@holoscopio.com> Subject: [Qemu-devel] [PATCH] mcf: add simr/cimr registers to interrupt controller for 5208 List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Thadeu Lima de Souza Cascardo The registers SIMR and CIMR allow interrupts to be masked/unsmasked without a read-modify-write. Linux m68knommu port uses this for some platforms. Without this patch, a m5208evb_defconfig won't boot. With this patch, I could get Linux to boot and get some output in the serial. Signed-off-by: Thadeu Lima de Souza Cascardo --- hw/mcf_intc.c | 18 ++++++++++++++++++ 1 files changed, 18 insertions(+), 0 deletions(-) diff --git a/hw/mcf_intc.c b/hw/mcf_intc.c index f01bd32..21c0f42 100644 --- a/hw/mcf_intc.c +++ b/hw/mcf_intc.c @@ -62,6 +62,10 @@ static uint32_t mcf_intc_read(void *opaque, target_phys_addr_t addr) return (uint32_t)(s->ifr >> 32); case 0x14: return (uint32_t)s->ifr; + /* Reading from SIMR and CIMR return 0 */ + case 0x1c: + case 0x1d: + return 0; case 0xe0: /* SWIACK. */ return s->active_vector; case 0xe1: case 0xe2: case 0xe3: case 0xe4: @@ -98,6 +102,20 @@ static void mcf_intc_write(void *opaque, target_phys_addr_t addr, uint32_t val) case 0x0c: s->imr = (s->imr & 0xffffffff00000000ull) | (uint32_t)val; break; + /* SIMR allows to easily mask interrupts */ + case 0x1c: + if (val & 0x40) + s->imr = ~0ull; + else + s->imr |= (1 << (val & 0x3f)); + break; + /* CIMR allows to easily unmask interrupts */ + case 0x1d: + if (val & 0x40) + s->imr = 0ull; + else + s->imr &= ~(1 << (val & 0x3f)); + break; default: hw_error("mcf_intc_write: Bad write offset %d\n", offset); break; -- 1.6.6.1