From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NzZQJ-0006Cv-85 for qemu-devel@nongnu.org; Wed, 07 Apr 2010 13:52:19 -0400 Received: from [140.186.70.92] (port=55404 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NzZQ5-00065d-F0 for qemu-devel@nongnu.org; Wed, 07 Apr 2010 13:52:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1NzZPm-0007LG-AQ for qemu-devel@nongnu.org; Wed, 07 Apr 2010 13:52:05 -0400 Received: from hall.aurel32.net ([88.191.82.174]:45324) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1NzZPj-0007K5-38 for qemu-devel@nongnu.org; Wed, 07 Apr 2010 13:51:44 -0400 From: Aurelien Jarno Date: Wed, 7 Apr 2010 19:51:22 +0200 Message-Id: <1270662685-7379-16-git-send-email-aurelien@aurel32.net> In-Reply-To: <1270662685-7379-1-git-send-email-aurelien@aurel32.net> References: <1270662685-7379-1-git-send-email-aurelien@aurel32.net> Subject: [Qemu-devel] [PATCH 15/18] tcg/arm: remove useless register tests in qemu_ld/st List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Andrzej Zaborowski , Aurelien Jarno addr_reg, data_reg and data_reg2 can't be register r0 or r1 du to the constraints. Don't check if they equals these registers. Signed-off-by: Aurelien Jarno --- tcg/arm/tcg-target.c | 30 ++++++++++-------------------- 1 files changed, 10 insertions(+), 20 deletions(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index 4b414ff..a4419f8 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -1030,10 +1030,8 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) # if TARGET_LONG_BITS == 32 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R1, 0, mem_index); # else - if (addr_reg2 != TCG_REG_R1) { - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, - TCG_REG_R1, 0, addr_reg2, SHIFT_IMM_LSL(0)); - } + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, + TCG_REG_R1, 0, addr_reg2, SHIFT_IMM_LSL(0)); tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R2, 0, mem_index); # endif tcg_out_bl(s, COND_AL, (tcg_target_long) qemu_ld_helpers[s_bits] - @@ -1239,10 +1237,8 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) tcg_out_b(s, COND_EQ, 8); /* TODO: move this code to where the constants pool will be */ - if (addr_reg != TCG_REG_R0) { - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, - TCG_REG_R0, 0, addr_reg, SHIFT_IMM_LSL(0)); - } + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, + TCG_REG_R0, 0, addr_reg, SHIFT_IMM_LSL(0)); # if TARGET_LONG_BITS == 32 switch (opc) { case 0: @@ -1254,17 +1250,13 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R2, 0, mem_index); break; case 2: - if (data_reg != TCG_REG_R1) { - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, - TCG_REG_R1, 0, data_reg, SHIFT_IMM_LSL(0)); - } + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, + TCG_REG_R1, 0, data_reg, SHIFT_IMM_LSL(0)); tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R2, 0, mem_index); break; case 3: - if (data_reg != TCG_REG_R1) { - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, - TCG_REG_R1, 0, data_reg, SHIFT_IMM_LSL(0)); - } + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, + TCG_REG_R1, 0, data_reg, SHIFT_IMM_LSL(0)); if (data_reg2 != TCG_REG_R2) { tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_R2, 0, data_reg2, SHIFT_IMM_LSL(0)); @@ -1273,10 +1265,8 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) break; } # else - if (addr_reg2 != TCG_REG_R1) { - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, - TCG_REG_R1, 0, addr_reg2, SHIFT_IMM_LSL(0)); - } + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, + TCG_REG_R1, 0, addr_reg2, SHIFT_IMM_LSL(0)); switch (opc) { case 0: tcg_out_ext8u(s, COND_AL, TCG_REG_R2, data_reg); -- 1.7.0.4