From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NzZQJ-0006Cl-2j for qemu-devel@nongnu.org; Wed, 07 Apr 2010 13:52:19 -0400 Received: from [140.186.70.92] (port=55426 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NzZQ8-000671-DQ for qemu-devel@nongnu.org; Wed, 07 Apr 2010 13:52:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1NzZPm-0007LK-Ad for qemu-devel@nongnu.org; Wed, 07 Apr 2010 13:52:08 -0400 Received: from hall.aurel32.net ([88.191.82.174]:45327) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1NzZPj-0007KL-Df for qemu-devel@nongnu.org; Wed, 07 Apr 2010 13:51:44 -0400 From: Aurelien Jarno Date: Wed, 7 Apr 2010 19:51:24 +0200 Message-Id: <1270662685-7379-18-git-send-email-aurelien@aurel32.net> In-Reply-To: <1270662685-7379-1-git-send-email-aurelien@aurel32.net> References: <1270662685-7379-1-git-send-email-aurelien@aurel32.net> Subject: [Qemu-devel] [PATCH 17/18] tcg/arm: optimize register allocation order List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Andrzej Zaborowski , Aurelien Jarno The beginning of the register allocation order list on the TCG arm target matches the list of clobbered registers. This means that when an helper is called, there is almost always clobbered registers that have to be spilled. Signed-off-by: Aurelien Jarno --- tcg/arm/tcg-target.c | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index 91542bd..03fe11c 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -65,10 +65,6 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { #endif static const int tcg_target_reg_alloc_order[] = { - TCG_REG_R0, - TCG_REG_R1, - TCG_REG_R2, - TCG_REG_R3, TCG_REG_R4, TCG_REG_R5, TCG_REG_R6, @@ -77,8 +73,12 @@ static const int tcg_target_reg_alloc_order[] = { TCG_REG_R9, TCG_REG_R10, TCG_REG_R11, - TCG_REG_R12, TCG_REG_R13, + TCG_REG_R0, + TCG_REG_R1, + TCG_REG_R2, + TCG_REG_R3, + TCG_REG_R12, TCG_REG_R14, }; -- 1.7.0.4