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From: Aurelien Jarno <aurelien@aurel32.net>
To: qemu-devel@nongnu.org
Cc: Andrzej Zaborowski <andrew.zaborowski@intel.com>,
	Aurelien Jarno <aurelien@aurel32.net>
Subject: [Qemu-devel] [PATCH v2 01/18] tcg/arm: remove SAVE_LR code
Date: Sat, 10 Apr 2010 03:32:49 +0200	[thread overview]
Message-ID: <1270863186-10180-2-git-send-email-aurelien@aurel32.net> (raw)
In-Reply-To: <1270863186-10180-1-git-send-email-aurelien@aurel32.net>

There is no need to save the LR register (r14) before a call to a
subroutine. According to the "Procedure Call Standard for the ARM
Architecture", it is the job of the callee to save this register.
Moreover, this register is already saved in the prologue/epilogue.

This patch removes the disabled SAVE_LR code, as there is no need to
reenable later.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 tcg/arm/tcg-target.c |   43 -------------------------------------------
 1 files changed, 0 insertions(+), 43 deletions(-)

diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index f0f669d..e86ed9a 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -748,10 +748,6 @@ static inline void tcg_out_call(TCGContext *s, int cond, uint32_t addr)
 {
     int32_t val;
 
-#ifdef SAVE_LR
-    tcg_out_dat_reg(s, cond, ARITH_MOV, TCG_REG_R8, 0, 14, SHIFT_IMM_LSL(0));
-#endif
-
     val = addr - (tcg_target_long) s->code_ptr;
     if (val < 0x01fffffd && val > -0x01fffffd)
         tcg_out_bl(s, cond, val);
@@ -770,23 +766,13 @@ static inline void tcg_out_call(TCGContext *s, int cond, uint32_t addr)
         }
 #endif
     }
-
-#ifdef SAVE_LR
-    tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));
-#endif
 }
 
 static inline void tcg_out_callr(TCGContext *s, int cond, int arg)
 {
-#ifdef SAVE_LR
-    tcg_out_dat_reg(s, cond, ARITH_MOV, TCG_REG_R8, 0, 14, SHIFT_IMM_LSL(0));
-#endif
     /* TODO: on ARMv5 and ARMv6 replace with tcg_out_blx(s, cond, arg);  */
     tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, 15, SHIFT_IMM_LSL(0));
     tcg_out_bx(s, cond, arg);
-#ifdef SAVE_LR
-    tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));
-#endif
 }
 
 static inline void tcg_out_goto_label(TCGContext *s, int cond, int label_index)
@@ -922,10 +908,6 @@ static inline void tcg_out_qemu_ld(TCGContext *s, int cond,
     label_ptr = (void *) s->code_ptr;
     tcg_out_b(s, COND_EQ, 8);
 
-# ifdef SAVE_LR
-    tcg_out_dat_reg(s, cond, ARITH_MOV, 8, 0, 14, SHIFT_IMM_LSL(0));
-# endif
-
     /* TODO: move this code to where the constants pool will be */
     if (addr_reg)
         tcg_out_dat_reg(s, cond, ARITH_MOV,
@@ -972,10 +954,6 @@ static inline void tcg_out_qemu_ld(TCGContext *s, int cond,
         break;
     }
 
-# ifdef SAVE_LR
-    tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, 8, SHIFT_IMM_LSL(0));
-# endif
-
     *label_ptr += ((void *) s->code_ptr - (void *) label_ptr - 8) >> 2;
 #else /* !CONFIG_SOFTMMU */
     if (GUEST_BASE) {
@@ -1186,10 +1164,6 @@ static inline void tcg_out_qemu_st(TCGContext *s, int cond,
     }
 # endif
 
-# ifdef SAVE_LR
-    tcg_out_dat_reg(s, cond, ARITH_MOV, 8, 0, 14, SHIFT_IMM_LSL(0));
-# endif
-
     tcg_out_bl(s, cond, (tcg_target_long) qemu_st_helpers[s_bits] -
                     (tcg_target_long) s->code_ptr);
 # if TARGET_LONG_BITS == 64
@@ -1197,10 +1171,6 @@ static inline void tcg_out_qemu_st(TCGContext *s, int cond,
         tcg_out_dat_imm(s, cond, ARITH_ADD, 13, 13, 0x10);
 # endif
 
-# ifdef SAVE_LR
-    tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, 8, SHIFT_IMM_LSL(0));
-# endif
-
     *label_ptr += ((void *) s->code_ptr - (void *) label_ptr - 8) >> 2;
 #else /* !CONFIG_SOFTMMU */
     if (GUEST_BASE) {
@@ -1254,15 +1224,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
 
     switch (opc) {
     case INDEX_op_exit_tb:
-#ifdef SAVE_LR
-        if (args[0] >> 8)
-            tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, 15, 0);
-        else
-            tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R0, 0, args[0]);
-        tcg_out_dat_reg(s, COND_AL, ARITH_MOV, 15, 0, 14, SHIFT_IMM_LSL(0));
-        if (args[0] >> 8)
-            tcg_out32(s, args[0]);
-#else
         {
             uint8_t *ld_ptr = s->code_ptr;
             if (args[0] >> 8)
@@ -1275,7 +1236,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
                 tcg_out32(s, args[0]);
             }
         }
-#endif
         break;
     case INDEX_op_goto_tb:
         if (s->tb_jmp_offset) {
@@ -1627,9 +1587,6 @@ void tcg_target_init(TCGContext *s)
                     (1 << TCG_REG_R12) | (1 << TCG_REG_R14));
 
     tcg_regset_clear(s->reserved_regs);
-#ifdef SAVE_LR
-    tcg_regset_set_reg(s->reserved_regs, TCG_REG_R14);
-#endif
     tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
     tcg_regset_set_reg(s->reserved_regs, TCG_REG_R8);
 
-- 
1.7.0.4

  reply	other threads:[~2010-04-10  1:33 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-04-10  1:32 [Qemu-devel] [PATCH v2 0/18] tcg/arm: cleanup and improvements Aurelien Jarno
2010-04-10  1:32 ` Aurelien Jarno [this message]
2010-04-10  1:32 ` [Qemu-devel] [PATCH v2 02/18] tcg/arm: explicitely list clobbered/reserved regs Aurelien Jarno
2010-04-10  1:32 ` [Qemu-devel] [PATCH v2 03/18] tcg/arm: remove store signed functions Aurelien Jarno
2010-04-10  1:32 ` [Qemu-devel] [PATCH v2 04/18] tcg/arm: replace integer values by registers enum Aurelien Jarno
2010-04-10  1:32 ` [Qemu-devel] [PATCH v2 05/18] tcg/arm: align 64-bit arguments in function calls Aurelien Jarno
2010-04-10  1:32 ` [Qemu-devel] [PATCH v2 06/18] tcg/arm: add variables to define the allowed instructions set Aurelien Jarno
2010-04-10  1:32 ` [Qemu-devel] [PATCH v2 07/18] tcg/arm: sxtb and sxth are available starting with ARMv6 Aurelien Jarno
2010-04-10  1:32 ` [Qemu-devel] [PATCH v2 08/18] tcg/arm: use the blx instruction when possible Aurelien Jarno
2010-04-10  1:32 ` [Qemu-devel] [PATCH v2 09/18] tcg/arm: add rotation ops Aurelien Jarno
2010-04-10  1:32 ` [Qemu-devel] [PATCH v2 10/18] tcg/arm: add ext16u op Aurelien Jarno
2010-04-10  1:32 ` [Qemu-devel] [PATCH v2 11/18] tcg/arm: add bswap ops Aurelien Jarno
2010-04-10  1:33 ` [Qemu-devel] [PATCH v2 12/18] tcg/arm: remove conditional argument for qemu_ld/st Aurelien Jarno
2010-04-10  1:33 ` [Qemu-devel] [PATCH v2 13/18] tcg/arm: use ext* ops in qemu_ld Aurelien Jarno
2010-04-10  1:33 ` [Qemu-devel] [PATCH v2 14/18] tcg/arm: bswap arguments in qemu_ld/st if needed Aurelien Jarno
2010-04-10  1:33 ` [Qemu-devel] [PATCH v2 15/18] tcg/arm: remove useless register tests in qemu_ld/st Aurelien Jarno
2010-04-10  1:33 ` [Qemu-devel] [PATCH v2 16/18] tcg/arm: fix argument alignment in qemu_st64 Aurelien Jarno
2010-04-10  1:33 ` [Qemu-devel] [PATCH v2 17/18] tcg/arm: optimize register allocation order Aurelien Jarno
2010-04-10  1:33 ` [Qemu-devel] [PATCH v2 18/18] tcg/arm: don't try to load constants using pc Aurelien Jarno

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