From: Aurelien Jarno <aurelien@aurel32.net>
To: qemu-devel@nongnu.org
Cc: Andrzej Zaborowski <andrew.zaborowski@intel.com>,
Aurelien Jarno <aurelien@aurel32.net>
Subject: [Qemu-devel] [PATCH v2 03/18] tcg/arm: remove store signed functions
Date: Sat, 10 Apr 2010 03:32:51 +0200 [thread overview]
Message-ID: <1270863186-10180-4-git-send-email-aurelien@aurel32.net> (raw)
In-Reply-To: <1270863186-10180-1-git-send-email-aurelien@aurel32.net>
Store signed functions doesn't make sense, and are not used. Remove
them.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
tcg/arm/tcg-target.c | 72 +++++++-------------------------------------------
1 files changed, 10 insertions(+), 62 deletions(-)
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 35f6c47..e923330 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -499,7 +499,7 @@ static inline void tcg_out_ld16u_8(TCGContext *s, int cond,
(((-im) & 0xf0) << 4) | ((-im) & 0xf));
}
-static inline void tcg_out_st16u_8(TCGContext *s, int cond,
+static inline void tcg_out_st16_8(TCGContext *s, int cond,
int rd, int rn, tcg_target_long im)
{
if (im >= 0)
@@ -519,7 +519,7 @@ static inline void tcg_out_ld16u_r(TCGContext *s, int cond,
(rn << 16) | (rd << 12) | rm);
}
-static inline void tcg_out_st16u_r(TCGContext *s, int cond,
+static inline void tcg_out_st16_r(TCGContext *s, int cond,
int rd, int rn, int rm)
{
tcg_out32(s, (cond << 28) | 0x018000b0 |
@@ -539,19 +539,6 @@ static inline void tcg_out_ld16s_8(TCGContext *s, int cond,
(((-im) & 0xf0) << 4) | ((-im) & 0xf));
}
-static inline void tcg_out_st16s_8(TCGContext *s, int cond,
- int rd, int rn, tcg_target_long im)
-{
- if (im >= 0)
- tcg_out32(s, (cond << 28) | 0x01c000f0 |
- (rn << 16) | (rd << 12) |
- ((im & 0xf0) << 4) | (im & 0xf));
- else
- tcg_out32(s, (cond << 28) | 0x014000f0 |
- (rn << 16) | (rd << 12) |
- (((-im) & 0xf0) << 4) | ((-im) & 0xf));
-}
-
static inline void tcg_out_ld16s_r(TCGContext *s, int cond,
int rd, int rn, int rm)
{
@@ -559,13 +546,6 @@ static inline void tcg_out_ld16s_r(TCGContext *s, int cond,
(rn << 16) | (rd << 12) | rm);
}
-static inline void tcg_out_st16s_r(TCGContext *s, int cond,
- int rd, int rn, int rm)
-{
- tcg_out32(s, (cond << 28) | 0x018000f0 |
- (rn << 16) | (rd << 12) | rm);
-}
-
static inline void tcg_out_ld8_12(TCGContext *s, int cond,
int rd, int rn, tcg_target_long im)
{
@@ -615,19 +595,6 @@ static inline void tcg_out_ld8s_8(TCGContext *s, int cond,
(((-im) & 0xf0) << 4) | ((-im) & 0xf));
}
-static inline void tcg_out_st8s_8(TCGContext *s, int cond,
- int rd, int rn, tcg_target_long im)
-{
- if (im >= 0)
- tcg_out32(s, (cond << 28) | 0x01c000d0 |
- (rn << 16) | (rd << 12) |
- ((im & 0xf0) << 4) | (im & 0xf));
- else
- tcg_out32(s, (cond << 28) | 0x014000d0 |
- (rn << 16) | (rd << 12) |
- (((-im) & 0xf0) << 4) | ((-im) & 0xf));
-}
-
static inline void tcg_out_ld8s_r(TCGContext *s, int cond,
int rd, int rn, int rm)
{
@@ -635,13 +602,6 @@ static inline void tcg_out_ld8s_r(TCGContext *s, int cond,
(rn << 16) | (rd << 12) | rm);
}
-static inline void tcg_out_st8s_r(TCGContext *s, int cond,
- int rd, int rn, int rm)
-{
- tcg_out32(s, (cond << 28) | 0x018000d0 |
- (rn << 16) | (rd << 12) | rm);
-}
-
static inline void tcg_out_ld32u(TCGContext *s, int cond,
int rd, int rn, int32_t offset)
{
@@ -682,14 +642,14 @@ static inline void tcg_out_ld16s(TCGContext *s, int cond,
tcg_out_ld16s_8(s, cond, rd, rn, offset);
}
-static inline void tcg_out_st16u(TCGContext *s, int cond,
+static inline void tcg_out_st16(TCGContext *s, int cond,
int rd, int rn, int32_t offset)
{
if (offset > 0xff || offset < -0xff) {
tcg_out_movi32(s, cond, TCG_REG_R8, offset);
- tcg_out_st16u_r(s, cond, rd, rn, TCG_REG_R8);
+ tcg_out_st16_r(s, cond, rd, rn, TCG_REG_R8);
} else
- tcg_out_st16u_8(s, cond, rd, rn, offset);
+ tcg_out_st16_8(s, cond, rd, rn, offset);
}
static inline void tcg_out_ld8u(TCGContext *s, int cond,
@@ -712,7 +672,7 @@ static inline void tcg_out_ld8s(TCGContext *s, int cond,
tcg_out_ld8s_8(s, cond, rd, rn, offset);
}
-static inline void tcg_out_st8u(TCGContext *s, int cond,
+static inline void tcg_out_st8(TCGContext *s, int cond,
int rd, int rn, int32_t offset)
{
if (offset > 0xfff || offset < -0xfff) {
@@ -1075,14 +1035,8 @@ static inline void tcg_out_qemu_st(TCGContext *s, int cond,
case 0:
tcg_out_st8_r(s, COND_EQ, data_reg, addr_reg, 1);
break;
- case 0 | 4:
- tcg_out_st8s_r(s, COND_EQ, data_reg, addr_reg, 1);
- break;
case 1:
- tcg_out_st16u_r(s, COND_EQ, data_reg, addr_reg, 1);
- break;
- case 1 | 4:
- tcg_out_st16s_r(s, COND_EQ, data_reg, addr_reg, 1);
+ tcg_out_st16_r(s, COND_EQ, data_reg, addr_reg, 1);
break;
case 2:
default:
@@ -1193,14 +1147,8 @@ static inline void tcg_out_qemu_st(TCGContext *s, int cond,
case 0:
tcg_out_st8_12(s, COND_AL, data_reg, addr_reg, 0);
break;
- case 0 | 4:
- tcg_out_st8s_8(s, COND_AL, data_reg, addr_reg, 0);
- break;
case 1:
- tcg_out_st16u_8(s, COND_AL, data_reg, addr_reg, 0);
- break;
- case 1 | 4:
- tcg_out_st16s_8(s, COND_AL, data_reg, addr_reg, 0);
+ tcg_out_st16_8(s, COND_AL, data_reg, addr_reg, 0);
break;
case 2:
default:
@@ -1299,10 +1247,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]);
break;
case INDEX_op_st8_i32:
- tcg_out_st8u(s, COND_AL, args[0], args[1], args[2]);
+ tcg_out_st8(s, COND_AL, args[0], args[1], args[2]);
break;
case INDEX_op_st16_i32:
- tcg_out_st16u(s, COND_AL, args[0], args[1], args[2]);
+ tcg_out_st16(s, COND_AL, args[0], args[1], args[2]);
break;
case INDEX_op_st_i32:
tcg_out_st32(s, COND_AL, args[0], args[1], args[2]);
--
1.7.0.4
next prev parent reply other threads:[~2010-04-10 1:33 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-04-10 1:32 [Qemu-devel] [PATCH v2 0/18] tcg/arm: cleanup and improvements Aurelien Jarno
2010-04-10 1:32 ` [Qemu-devel] [PATCH v2 01/18] tcg/arm: remove SAVE_LR code Aurelien Jarno
2010-04-10 1:32 ` [Qemu-devel] [PATCH v2 02/18] tcg/arm: explicitely list clobbered/reserved regs Aurelien Jarno
2010-04-10 1:32 ` Aurelien Jarno [this message]
2010-04-10 1:32 ` [Qemu-devel] [PATCH v2 04/18] tcg/arm: replace integer values by registers enum Aurelien Jarno
2010-04-10 1:32 ` [Qemu-devel] [PATCH v2 05/18] tcg/arm: align 64-bit arguments in function calls Aurelien Jarno
2010-04-10 1:32 ` [Qemu-devel] [PATCH v2 06/18] tcg/arm: add variables to define the allowed instructions set Aurelien Jarno
2010-04-10 1:32 ` [Qemu-devel] [PATCH v2 07/18] tcg/arm: sxtb and sxth are available starting with ARMv6 Aurelien Jarno
2010-04-10 1:32 ` [Qemu-devel] [PATCH v2 08/18] tcg/arm: use the blx instruction when possible Aurelien Jarno
2010-04-10 1:32 ` [Qemu-devel] [PATCH v2 09/18] tcg/arm: add rotation ops Aurelien Jarno
2010-04-10 1:32 ` [Qemu-devel] [PATCH v2 10/18] tcg/arm: add ext16u op Aurelien Jarno
2010-04-10 1:32 ` [Qemu-devel] [PATCH v2 11/18] tcg/arm: add bswap ops Aurelien Jarno
2010-04-10 1:33 ` [Qemu-devel] [PATCH v2 12/18] tcg/arm: remove conditional argument for qemu_ld/st Aurelien Jarno
2010-04-10 1:33 ` [Qemu-devel] [PATCH v2 13/18] tcg/arm: use ext* ops in qemu_ld Aurelien Jarno
2010-04-10 1:33 ` [Qemu-devel] [PATCH v2 14/18] tcg/arm: bswap arguments in qemu_ld/st if needed Aurelien Jarno
2010-04-10 1:33 ` [Qemu-devel] [PATCH v2 15/18] tcg/arm: remove useless register tests in qemu_ld/st Aurelien Jarno
2010-04-10 1:33 ` [Qemu-devel] [PATCH v2 16/18] tcg/arm: fix argument alignment in qemu_st64 Aurelien Jarno
2010-04-10 1:33 ` [Qemu-devel] [PATCH v2 17/18] tcg/arm: optimize register allocation order Aurelien Jarno
2010-04-10 1:33 ` [Qemu-devel] [PATCH v2 18/18] tcg/arm: don't try to load constants using pc Aurelien Jarno
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