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From: Aurelien Jarno <aurelien@aurel32.net>
To: qemu-devel@nongnu.org
Cc: Andrzej Zaborowski <andrew.zaborowski@intel.com>,
	Aurelien Jarno <aurelien@aurel32.net>
Subject: [Qemu-devel] [PATCH v2 06/18] tcg/arm: add variables to define the allowed instructions set
Date: Sat, 10 Apr 2010 03:32:54 +0200	[thread overview]
Message-ID: <1270863186-10180-7-git-send-email-aurelien@aurel32.net> (raw)
In-Reply-To: <1270863186-10180-1-git-send-email-aurelien@aurel32.net>

Use a set of variables to define the allowed ARM instructions, depending
on the __ARM_ARCH_*__ GCC defines.

v1 -> v2:
- switch from #defines to variables
- reorder and factorize definitions
- add more architectures

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 tcg/arm/tcg-target.c |  123 ++++++++++++++++++++++++++++++++++----------------
 1 files changed, 84 insertions(+), 39 deletions(-)

diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index ee5f723..2d834d6 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -22,6 +22,51 @@
  * THE SOFTWARE.
  */
 
+#if defined(__ARM_ARCH_7__) ||  \
+    defined(__ARM_ARCH_7A__) || \
+    defined(__ARM_ARCH_7EM__) || \
+    defined(__ARM_ARCH_7M__) || \
+    defined(__ARM_ARCH_7R__)
+#define USE_ARMV7_INSTRUCTIONS
+#endif
+
+#if defined(USE_ARMV7_INSTRUCTIONS) || \
+    defined(__ARM_ARCH_6J__) || \
+    defined(__ARM_ARCH_6K__) || \
+    defined(__ARM_ARCH_6Z__) || \
+    defined(__ARM_ARCH_6ZK__) || \
+    defined(__ARM_ARCH_T2__)
+#define USE_ARMV6_INSTRUCTIONS
+#endif
+
+#if defined(USE_ARMV6_INSTRUCTIONS) || \
+    defined(__ARM_ARCH_5T__) || \
+    defined(__ARM_ARCH_5TE__) || \
+    defined(__ARM_ARCH_5TEJ__)
+#define USE_ARMV5_INSTRUCTIONS
+#endif
+
+#ifdef USE_ARMV5_INSTRUCTIONS
+static const int use_armv5_instructions = 1;
+#else
+static const int use_armv5_instructions = 0;
+#endif
+#undef USE_ARMV5_INSTRUCTIONS
+
+#ifdef USE_ARMV6_INSTRUCTIONS
+static const int use_armv6_instructions = 1;
+#else
+static const int use_armv6_instructions = 0;
+#endif
+#undef USE_ARMV6_INSTRUCTIONS
+
+#ifdef USE_ARMV7_INSTRUCTIONS
+static const int use_armv7_instructions = 1;
+#else
+static const int use_armv7_instructions = 0;
+#endif
+#undef USE_ARMV7_INSTRUCTIONS
+
 #ifndef NDEBUG
 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
     "%r0",
@@ -361,27 +406,27 @@ static inline void tcg_out_movi32(TCGContext *s,
                 tcg_out_dat_imm(s, cond, ARITH_ADD, rd, 15, offset) :
                 tcg_out_dat_imm(s, cond, ARITH_SUB, rd, 15, -offset);
 
-#ifdef __ARM_ARCH_7A__
-    /* use movw/movt */
-    /* movw */
-    tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12)
-              | ((arg << 4) & 0x000f0000) | (arg & 0xfff));
-    if (arg & 0xffff0000)
-        /* movt */
-        tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12)
-                  | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff));
-#else
-    tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, arg & 0xff);
-    if (arg & 0x0000ff00)
-        tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
-                        ((arg >>  8) & 0xff) | 0xc00);
-    if (arg & 0x00ff0000)
-        tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
-                        ((arg >> 16) & 0xff) | 0x800);
-    if (arg & 0xff000000)
-        tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
-                        ((arg >> 24) & 0xff) | 0x400);
-#endif
+    if (use_armv7_instructions) {
+        /* use movw/movt */
+        /* movw */
+        tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12)
+                  | ((arg << 4) & 0x000f0000) | (arg & 0xfff));
+        if (arg & 0xffff0000)
+            /* movt */
+            tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12)
+                      | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff));
+    } else {
+        tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, arg & 0xff);
+        if (arg & 0x0000ff00)
+            tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
+                            ((arg >>  8) & 0xff) | 0xc00);
+        if (arg & 0x00ff0000)
+            tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
+                            ((arg >> 16) & 0xff) | 0x800);
+        if (arg & 0xff000000)
+            tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
+                            ((arg >> 24) & 0xff) | 0x400);
+        }
 }
 
 static inline void tcg_out_mul32(TCGContext *s,
@@ -1433,26 +1478,26 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
         break;
 
     case INDEX_op_ext8s_i32:
-#ifdef __ARM_ARCH_7A__
-        /* sxtb */
-        tcg_out32(s, 0xe6af0070 | (args[0] << 12) | args[1]);
-#else
-        tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
-                        args[0], 0, args[1], SHIFT_IMM_LSL(24));
-        tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
-                        args[0], 0, args[0], SHIFT_IMM_ASR(24));
-#endif
+        if (use_armv7_instructions) {
+            /* sxtb */
+            tcg_out32(s, 0xe6af0070 | (args[0] << 12) | args[1]);
+        } else {
+            tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
+                            args[0], 0, args[1], SHIFT_IMM_LSL(24));
+            tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
+                            args[0], 0, args[0], SHIFT_IMM_ASR(24));
+        }
         break;
     case INDEX_op_ext16s_i32:
-#ifdef __ARM_ARCH_7A__
-        /* sxth */
-        tcg_out32(s, 0xe6bf0070 | (args[0] << 12) | args[1]);
-#else
-        tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
-                        args[0], 0, args[1], SHIFT_IMM_LSL(16));
-        tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
-                        args[0], 0, args[0], SHIFT_IMM_ASR(16));
-#endif
+        if (use_armv7_instructions) {
+            /* sxth */
+            tcg_out32(s, 0xe6bf0070 | (args[0] << 12) | args[1]);
+        } else {
+            tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
+                            args[0], 0, args[1], SHIFT_IMM_LSL(16));
+            tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
+                            args[0], 0, args[0], SHIFT_IMM_ASR(16));
+        }
         break;
 
     default:
-- 
1.7.0.4

  parent reply	other threads:[~2010-04-10  1:33 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-04-10  1:32 [Qemu-devel] [PATCH v2 0/18] tcg/arm: cleanup and improvements Aurelien Jarno
2010-04-10  1:32 ` [Qemu-devel] [PATCH v2 01/18] tcg/arm: remove SAVE_LR code Aurelien Jarno
2010-04-10  1:32 ` [Qemu-devel] [PATCH v2 02/18] tcg/arm: explicitely list clobbered/reserved regs Aurelien Jarno
2010-04-10  1:32 ` [Qemu-devel] [PATCH v2 03/18] tcg/arm: remove store signed functions Aurelien Jarno
2010-04-10  1:32 ` [Qemu-devel] [PATCH v2 04/18] tcg/arm: replace integer values by registers enum Aurelien Jarno
2010-04-10  1:32 ` [Qemu-devel] [PATCH v2 05/18] tcg/arm: align 64-bit arguments in function calls Aurelien Jarno
2010-04-10  1:32 ` Aurelien Jarno [this message]
2010-04-10  1:32 ` [Qemu-devel] [PATCH v2 07/18] tcg/arm: sxtb and sxth are available starting with ARMv6 Aurelien Jarno
2010-04-10  1:32 ` [Qemu-devel] [PATCH v2 08/18] tcg/arm: use the blx instruction when possible Aurelien Jarno
2010-04-10  1:32 ` [Qemu-devel] [PATCH v2 09/18] tcg/arm: add rotation ops Aurelien Jarno
2010-04-10  1:32 ` [Qemu-devel] [PATCH v2 10/18] tcg/arm: add ext16u op Aurelien Jarno
2010-04-10  1:32 ` [Qemu-devel] [PATCH v2 11/18] tcg/arm: add bswap ops Aurelien Jarno
2010-04-10  1:33 ` [Qemu-devel] [PATCH v2 12/18] tcg/arm: remove conditional argument for qemu_ld/st Aurelien Jarno
2010-04-10  1:33 ` [Qemu-devel] [PATCH v2 13/18] tcg/arm: use ext* ops in qemu_ld Aurelien Jarno
2010-04-10  1:33 ` [Qemu-devel] [PATCH v2 14/18] tcg/arm: bswap arguments in qemu_ld/st if needed Aurelien Jarno
2010-04-10  1:33 ` [Qemu-devel] [PATCH v2 15/18] tcg/arm: remove useless register tests in qemu_ld/st Aurelien Jarno
2010-04-10  1:33 ` [Qemu-devel] [PATCH v2 16/18] tcg/arm: fix argument alignment in qemu_st64 Aurelien Jarno
2010-04-10  1:33 ` [Qemu-devel] [PATCH v2 17/18] tcg/arm: optimize register allocation order Aurelien Jarno
2010-04-10  1:33 ` [Qemu-devel] [PATCH v2 18/18] tcg/arm: don't try to load constants using pc Aurelien Jarno

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