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From: Cam Macdonell <cam@cs.ualberta.ca>
To: kvm@vger.kernel.org
Cc: Cam Macdonell <cam@cs.ualberta.ca>, qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH v5 1/5] Device specification for shared memory PCI device
Date: Wed, 21 Apr 2010 11:53:25 -0600	[thread overview]
Message-ID: <1271872408-22842-2-git-send-email-cam@cs.ualberta.ca> (raw)
In-Reply-To: <1271872408-22842-1-git-send-email-cam@cs.ualberta.ca>

---
 docs/specs/ivshmem_device_spec.txt |   91 ++++++++++++++++++++++++++++++++++++
 1 files changed, 91 insertions(+), 0 deletions(-)
 create mode 100644 docs/specs/ivshmem_device_spec.txt

diff --git a/docs/specs/ivshmem_device_spec.txt b/docs/specs/ivshmem_device_spec.txt
new file mode 100644
index 0000000..b955b22
--- /dev/null
+++ b/docs/specs/ivshmem_device_spec.txt
@@ -0,0 +1,91 @@
+
+Device Specification for Inter-VM shared memory device
+------------------------------------------------------
+
+The Inter-VM shared memory device is designed to share a region of memory to
+userspace in multiple virtual guests.  The memory region does not belong to any
+guest, but is a POSIX memory object on the host.  Optionally, the device may
+support sending interrupts to other guests sharing the same memory region.
+
+
+The Inter-VM PCI device
+-----------------------
+
+*BARs*
+
+The device supports three BARs.  BAR0 is a 1 Kbyte MMIO region to support
+registers.  BAR1 is used for MSI-X when it is enabled in the device.  BAR2 is
+used to map the shared memory object from the host.  The size of BAR2 is
+specified when the guest is started and must be a power of 2 in size.
+
+*Registers*
+
+The device currently supports 4 registers of 32-bits each.  Registers
+are used for synchronization between guests sharing the same memory object when
+interrupts are supported (this requires using the shared memory server).
+
+The server assigns each VM an ID number and sends this ID number to the Qemu
+process when the guest starts.
+
+enum ivshmem_registers {
+    IntrMask = 0,
+    IntrStatus = 4,
+    IVPosition = 8,
+    Doorbell = 12
+};
+
+The first two registers are the interrupt mask and status registers.  Mask and
+status are only used with pin-based interrupts.  They are unused with MSI
+interrupts.
+
+Status Register: The status register is set to 1 when an interrupt occurs.
+
+Mask Register: The mask register is bitwise ANDed with the interrupt status
+and the result will raise an interrupt if it is non-zero.  However, since 1 is
+the only value the status will be set to, it is only the first bit of the mask
+that has any effect.  Therefore interrupts can be masked by setting the first
+bit to 0 and unmasked by setting the first bit to 1.
+
+IVPosition Register: The IVPosition register is read-only and reports the
+guest's ID number.
+
+Doorbell Register:  To interrupt another guest, a guest must write to the
+Doorbell register.  The doorbell register is 32-bits, logically divided into
+two 16-bit fields.  The high 16-bits are the guest ID to interrupt and the low
+16-bits are the interrupt vector to trigger.  The semantics of the value
+written to the doorbell depends on whether the device is using MSI or a regular
+pin-based interrupt.  In short, MSI uses vectors while regular interrupts set the
+status register.
+
+Regular Interrupts
+
+If regular interrupts are used (due to either a guest not supporting MSI or the
+user specifying not to use them on startup) then the value written to the lower
+16-bits of the Doorbell register results is arbitrary and will trigger an
+interrupt in the destination guest.
+
+Message Signalled Interrupts
+
+A ivshmem device may support multiple MSI vectors.  If so, the lower 16-bits
+written to the Doorbell register must be between 0 and the maximum number of
+vectors the guest supports.  The lower 16 bits written to the doorbell is the
+MSI vector that will be raised in the destination guest.  The number of MSI
+vectors is configurable but it is set when the VM is started.
+
+The important thing to remember with MSI is that it is only a signal, no status
+is set (since MSI interrupts are not shared).  All information other than the
+interrupt itself should be communicated via the shared memory region.  Devices
+supporting multiple MSI vectors can use different vectors to indicate different
+events have occurred.  The semantics of interrupt vectors are left to the
+user's discretion.
+
+
+Usage in the Guest
+------------------
+
+The shared memory device is intended to be used with the provided UIO driver.
+Very little configuration is needed.  The guest should map BAR0 to access the
+registers (an array of 32-bit ints allows simple writing) and map BAR2 to
+access the shared memory region itself.  The size of the shared memory region
+is specified when the guest (or shared memory server) is started.  A guest may
+map the whole shared memory region or only part of it.
-- 
1.6.2.5

  reply	other threads:[~2010-04-21 17:53 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-04-21 17:53 [Qemu-devel] [PATCH v5 0/5] PCI Shared Memory device Cam Macdonell
2010-04-21 17:53 ` Cam Macdonell [this message]
2010-04-21 17:53   ` [Qemu-devel] [PATCH v5 2/5] Support adding a file to qemu's ram allocation Cam Macdonell
2010-04-21 17:53     ` [Qemu-devel] [PATCH v5 3/5] Add functions for assigning ioeventfd and irqfds Cam Macdonell
2010-04-21 17:53       ` [Qemu-devel] [PATCH v5 4/5] Inter-VM shared memory PCI device Cam Macdonell
2010-04-21 18:00         ` [Qemu-devel] [PATCH v5 5/5] shared memory server for inter-VM shared memory Cam Macdonell
2010-05-05 16:57         ` [Qemu-devel] [PATCH v5 4/5] RESEND: Inter-VM shared memory PCI device Cam Macdonell
2010-05-06 17:32         ` [Qemu-devel] Re: [PATCH v5 4/5] " Anthony Liguori
2010-05-06 17:59           ` Cam Macdonell
2010-05-10 11:59         ` Avi Kivity
2010-05-10 15:22           ` Cam Macdonell
2010-05-10 15:28             ` Avi Kivity
2010-05-10 15:38               ` Anthony Liguori
2010-05-10 16:20                 ` Cam Macdonell
2010-05-10 16:52                   ` Anthony Liguori
2010-05-18 16:58                     ` Cam Macdonell
2010-05-18 17:27                       ` Avi Kivity
2010-05-10 16:59                 ` Avi Kivity
2010-05-10 17:25                   ` Anthony Liguori
2010-05-10 17:43                     ` Cam Macdonell
2010-05-10 17:52                       ` Anthony Liguori
2010-05-10 18:01                         ` Cam Macdonell
2010-05-11  7:59                         ` Avi Kivity
2010-05-11 13:10                           ` Anthony Liguori
2010-05-11 14:03                             ` Avi Kivity
2010-05-11 14:17                               ` Cam Macdonell
2010-05-11 14:53                                 ` Avi Kivity
2010-05-11 15:51                                   ` Anthony Liguori
2010-05-11 16:39                                     ` Cam Macdonell
2010-05-11 17:05                                       ` Anthony Liguori
2010-05-11 17:50                                         ` Cam Macdonell
2010-05-11 18:13                                         ` Avi Kivity
2010-05-12 15:32                                           ` Cam Macdonell
2010-05-12 15:48                                             ` Avi Kivity
2010-05-11 18:09                                     ` Avi Kivity
2010-05-11  7:55                     ` Avi Kivity
2010-05-10 15:41               ` Cam Macdonell
2010-05-10 16:40                 ` Avi Kivity
2010-05-10 16:48                   ` Cam Macdonell
2010-05-12 15:49                     ` Avi Kivity
2010-05-12 16:14                       ` Cam Macdonell
2010-05-12 16:45                         ` Avi Kivity
2010-05-10 23:17           ` Cam Macdonell
2010-05-11  8:03             ` Avi Kivity
2010-05-13 21:10           ` Cam Macdonell
2010-05-15  6:05             ` Avi Kivity
2010-05-10 10:43       ` [Qemu-devel] Re: [PATCH v5 3/5] Add functions for assigning ioeventfd and irqfds Avi Kivity
2010-05-10 15:13         ` Cam Macdonell
2010-05-10 15:17           ` Avi Kivity
2010-05-10 10:39     ` [Qemu-devel] Re: [PATCH v5 2/5] Support adding a file to qemu's ram allocation Avi Kivity
2010-05-10 15:32       ` Cam Macdonell

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