From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1O8VoJ-0003F0-RZ for qemu-devel@nongnu.org; Sun, 02 May 2010 05:50:03 -0400 Received: from [140.186.70.92] (port=36352 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1O8VoG-0003Eb-Kj for qemu-devel@nongnu.org; Sun, 02 May 2010 05:50:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1O8VoE-0007qK-U9 for qemu-devel@nongnu.org; Sun, 02 May 2010 05:50:00 -0400 Received: from mail-pw0-f45.google.com ([209.85.160.45]:33475) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1O8VoE-0007qA-PP for qemu-devel@nongnu.org; Sun, 02 May 2010 05:49:58 -0400 Received: by pwi6 with SMTP id 6so780217pwi.4 for ; Sun, 02 May 2010 02:49:56 -0700 (PDT) Sender: Rabin Vincent From: Rabin Vincent Date: Sun, 2 May 2010 15:20:51 +0530 Message-Id: <1272793852-26260-1-git-send-email-rabin@rab.in> Subject: [Qemu-devel] [PATCH 1/2] arm_timer: reload timer when enabled List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Rabin Vincent Reload the timer when TimerControl is written, if the timer is to be enabled. Otherwise, if an earlier write to TimerLoad was done while periodic mode was not set, s->delta may incorrectly still have the value of the maximum limit instead of the value written to TimerLoad. This problem is evident on versatileap on current linux-next, which enables TIMER_CTRL_32BIT before writing to TimerLoad and then enabling periodic mode and starting the timer. This causes the first periodic tick to be scheduled to occur after 0xffffffff periods, leading to a perceived hang while the kernel waits for the first timer tick. Signed-off-by: Rabin Vincent --- hw/arm_timer.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/hw/arm_timer.c b/hw/arm_timer.c index 9fef191..5b6947a 100644 --- a/hw/arm_timer.c +++ b/hw/arm_timer.c @@ -113,7 +113,7 @@ static void arm_timer_write(void *opaque, target_phys_addr_t offset, case 1: freq >>= 4; break; case 2: freq >>= 8; break; } - arm_timer_recalibrate(s, 0); + arm_timer_recalibrate(s, s->control & TIMER_CTRL_ENABLE); ptimer_set_freq(s->timer, freq); if (s->control & TIMER_CTRL_ENABLE) { /* Restart the timer if still enabled. */ -- 1.7.0.4