From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=44801 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OF770-000133-Rw for qemu-devel@nongnu.org; Thu, 20 May 2010 10:53:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OF76v-00080n-Av for qemu-devel@nongnu.org; Thu, 20 May 2010 10:52:38 -0400 Received: from mail.codesourcery.com ([38.113.113.100]:35482) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OF76u-00080K-V2 for qemu-devel@nongnu.org; Thu, 20 May 2010 10:52:33 -0400 From: Nathan Froyd Date: Thu, 20 May 2010 07:52:22 -0700 Message-Id: <1274367150-26576-3-git-send-email-froydnj@codesourcery.com> In-Reply-To: <1274367150-26576-1-git-send-email-froydnj@codesourcery.com> References: <1274367150-26576-1-git-send-email-froydnj@codesourcery.com> Subject: [Qemu-devel] [PATCH 02/10] target-mips: add microMIPS-specific bits to mips-defs.h List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aurelien@aurel32.net There's a new ASE_MICROMIPS instruction flag, and some extra CP0_Config3 fields. The ISA and ISA_ON_EXC fields are specific to microMIPS. The DSP2P is for version 2 of the DSP ASE. Signed-off-by: Nathan Froyd --- target-mips/cpu.h | 3 +++ target-mips/mips-defs.h | 1 + 2 files changed, 4 insertions(+), 0 deletions(-) diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 7285636..986d938 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -363,6 +363,9 @@ struct CPUMIPSState { #define CP0C2_SA 0 int32_t CP0_Config3; #define CP0C3_M 31 +#define CP0C3_ISA_ON_EXC 16 +#define CP0C3_ISA 14 +#define CP0C3_DSP2P 11 #define CP0C3_DSPP 10 #define CP0C3_LPA 7 #define CP0C3_VEIC 6 diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h index c57de02..a7f4697 100644 --- a/target-mips/mips-defs.h +++ b/target-mips/mips-defs.h @@ -38,6 +38,7 @@ #define ASE_DSPR2 0x00010000 #define ASE_MT 0x00020000 #define ASE_SMARTMIPS 0x00040000 +#define ASE_MICROMIPS 0x00080000 /* Chip specific instructions. */ #define INSN_VR54XX 0x80000000 -- 1.6.3.2