From: Nathan Froyd <froydnj@codesourcery.com>
To: qemu-devel@nongnu.org
Cc: aurelien@aurel32.net
Subject: [Qemu-devel] [PATCH 07/10] target-mips: add microMIPS CPUs
Date: Thu, 20 May 2010 07:52:27 -0700 [thread overview]
Message-ID: <1274367150-26576-8-git-send-email-froydnj@codesourcery.com> (raw)
In-Reply-To: <1274367150-26576-1-git-send-email-froydnj@codesourcery.com>
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
target-mips/translate_init.c | 61 ++++++++++++++++++++++++++++++++++++++++++
1 files changed, 61 insertions(+), 0 deletions(-)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index b79ed56..8e17f4b 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -141,6 +141,25 @@ static const mips_def_t mips_defs[] =
.mmu_type = MMU_TYPE_FMT,
},
{
+ .name = "4Km-micromips",
+ .CP0_PRid = 0x00018300,
+ /* Config1 implemented, fixed mapping MMU,
+ no virtual icache, uncached coherency. */
+ .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x1258FF17,
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
+ .mmu_type = MMU_TYPE_FMT,
+ },
+ {
.name = "4KEcR1",
.CP0_PRid = 0x00018400,
.CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
@@ -245,6 +264,25 @@ static const mips_def_t mips_defs[] =
.mmu_type = MMU_TYPE_R4000,
},
{
+ .name = "24Kc-micromips",
+ .CP0_PRid = 0x00019300,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ /* No DSP implemented. */
+ .CP0_Status_rw_bitmask = 0x1278FF1F,
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
.name = "24Kf",
.CP0_PRid = 0x00019300,
.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
@@ -269,6 +307,29 @@ static const mips_def_t mips_defs[] =
.mmu_type = MMU_TYPE_R4000,
},
{
+ .name = "24Kf-micromips",
+ .CP0_PRid = 0x00019300,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ /* No DSP implemented. */
+ .CP0_Status_rw_bitmask = 0x3678FF1F,
+ .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
+ (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
.name = "34Kf",
.CP0_PRid = 0x00019500,
.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
--
1.6.3.2
next prev parent reply other threads:[~2010-05-20 14:53 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-05-20 14:52 [Qemu-devel] [PATCH 00/10] target-mips: add microMIPS ASE support Nathan Froyd
2010-05-20 14:52 ` [Qemu-devel] [PATCH 01/10] target-mips: break out [ls][wd]c1 and rdhwr insn generation Nathan Froyd
2010-05-20 14:52 ` [Qemu-devel] [PATCH 02/10] target-mips: add microMIPS-specific bits to mips-defs.h Nathan Froyd
2010-05-20 14:52 ` [Qemu-devel] [PATCH 03/10] target-mips: add enum constants for various invocations of FOP Nathan Froyd
2010-05-20 14:52 ` [Qemu-devel] [PATCH 04/10] target-mips: refactor {c, abs}.cond.fmt insns Nathan Froyd
2010-05-20 15:34 ` Richard Henderson
2010-05-20 16:27 ` Nathan Froyd
2010-05-20 14:52 ` [Qemu-devel] [PATCH 05/10] target-mips: small changes to use new FMT_ enums Nathan Froyd
2010-05-20 14:52 ` [Qemu-devel] [PATCH 06/10] target-mips: add microMIPS ASE support Nathan Froyd
2010-05-20 14:52 ` Nathan Froyd [this message]
2010-05-20 14:52 ` [Qemu-devel] [PATCH 08/10] target-mips: add microMIPS exception handler support Nathan Froyd
2010-05-20 14:52 ` [Qemu-devel] [PATCH 09/10] linux-user: honor low bit of entry PC for MIPS Nathan Froyd
2010-05-20 14:52 ` [Qemu-devel] [PATCH 10/10] hw: honor low bit in mipssim machine Nathan Froyd
-- strict thread matches above, loose matches on Subject: below --
2010-05-24 16:19 [Qemu-devel] [PATCH 00/10] target-mips: add microMIPS ASE support, v2 Nathan Froyd
2010-05-24 16:19 ` [Qemu-devel] [PATCH 07/10] target-mips: add microMIPS CPUs Nathan Froyd
2010-06-04 18:35 ` Richard Henderson
2010-06-04 18:50 ` Nathan Froyd
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1274367150-26576-8-git-send-email-froydnj@codesourcery.com \
--to=froydnj@codesourcery.com \
--cc=aurelien@aurel32.net \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).