From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=48925 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OFkEY-0006Da-4Q for qemu-devel@nongnu.org; Sat, 22 May 2010 04:39:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OFkEW-0002zl-8p for qemu-devel@nongnu.org; Sat, 22 May 2010 04:39:01 -0400 Received: from fg-out-1718.google.com ([72.14.220.158]:46733) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OFkEV-0002zb-Ns for qemu-devel@nongnu.org; Sat, 22 May 2010 04:39:00 -0400 Received: by fg-out-1718.google.com with SMTP id 16so1086945fgg.10 for ; Sat, 22 May 2010 01:38:58 -0700 (PDT) From: Artyom Tarasenko Date: Sat, 22 May 2010 10:38:56 +0200 Message-Id: <1274517536-20889-1-git-send-email-atar4qemu@gmail.com> Subject: [Qemu-devel] [PATCH] sparc32 protect read-only bits in DMA CSR registers List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: blauwirbel@gmail.com, Artyom Tarasenko On a real hardware changing read-only bits has no effect Use a mask common for SCSI and Ethernet registers. The crucial bit is DMA_INTR, because setting or clearing it may produce spurious interrupts. This patch allows booting Solaris 2.3 --- hw/sparc32_dma.c | 12 ++++++++---- 1 files changed, 8 insertions(+), 4 deletions(-) diff --git a/hw/sparc32_dma.c b/hw/sparc32_dma.c index 3ceb851..b521707 100644 --- a/hw/sparc32_dma.c +++ b/hw/sparc32_dma.c @@ -62,6 +62,9 @@ #define DMA_DRAIN_FIFO 0x40 #define DMA_RESET 0x80 +/* XXX SCSI and ethernet should have different read-only bit masks */ +#define DMA_CSR_RO_MASK 0xfe000007 + typedef struct DMAState DMAState; struct DMAState { @@ -187,7 +190,7 @@ static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) switch (saddr) { case 0: if (val & DMA_INTREN) { - if (val & DMA_INTR) { + if (s->dmaregs[0] & DMA_INTR) { DPRINTF("Raise IRQ\n"); qemu_irq_raise(s->irq); } @@ -204,16 +207,17 @@ static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) val &= ~DMA_DRAIN_FIFO; } else if (val == 0) val = DMA_DRAIN_FIFO; - val &= 0x0fffffff; + val &= ~DMA_CSR_RO_MASK; val |= DMA_VER; + s->dmaregs[0] = (s->dmaregs[0] & DMA_CSR_RO_MASK) | val; break; case 1: s->dmaregs[0] |= DMA_LOADED; - break; + /* fall through */ default: + s->dmaregs[saddr] = val; break; } - s->dmaregs[saddr] = val; } static CPUReadMemoryFunc * const dma_mem_read[3] = { -- 1.6.2.5