* [Qemu-devel] [PATCH] sparc32 SuperSPARC MMU Breakpoint Action register (SS-20 OBP fix)
@ 2010-05-29 20:48 Artyom Tarasenko
2010-05-29 21:27 ` [Qemu-devel] " Blue Swirl
0 siblings, 1 reply; 2+ messages in thread
From: Artyom Tarasenko @ 2010-05-29 20:48 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, Artyom Tarasenko
SuperSPARC MMU Breakpoint Action register is used by OBP at boot
The patch allows booting Solaris and some other OS with
SPARCStation-20 OBP.
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
---
target-sparc/op_helper.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index aaacfc4..ef3504f 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -1745,6 +1745,7 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
case 0x31: // Turbosparc RAM snoop
case 0x32: // Turbosparc page table descriptor diagnostic
case 0x39: /* data cache diagnostic register */
+ case 0x4c: /* SuperSPARC MMU Breakpoint Action register */
ret = 0;
break;
case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
--
1.6.2.5
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [Qemu-devel] Re: [PATCH] sparc32 SuperSPARC MMU Breakpoint Action register (SS-20 OBP fix)
2010-05-29 20:48 [Qemu-devel] [PATCH] sparc32 SuperSPARC MMU Breakpoint Action register (SS-20 OBP fix) Artyom Tarasenko
@ 2010-05-29 21:27 ` Blue Swirl
0 siblings, 0 replies; 2+ messages in thread
From: Blue Swirl @ 2010-05-29 21:27 UTC (permalink / raw)
To: Artyom Tarasenko; +Cc: qemu-devel, Artyom Tarasenko
Thanks, applied.
On Sat, May 29, 2010 at 8:48 PM, Artyom Tarasenko
<atar4qemu@googlemail.com> wrote:
> SuperSPARC MMU Breakpoint Action register is used by OBP at boot
>
> The patch allows booting Solaris and some other OS with
> SPARCStation-20 OBP.
>
> Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
> ---
> target-sparc/op_helper.c | 1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
> index aaacfc4..ef3504f 100644
> --- a/target-sparc/op_helper.c
> +++ b/target-sparc/op_helper.c
> @@ -1745,6 +1745,7 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
> case 0x31: // Turbosparc RAM snoop
> case 0x32: // Turbosparc page table descriptor diagnostic
> case 0x39: /* data cache diagnostic register */
> + case 0x4c: /* SuperSPARC MMU Breakpoint Action register */
> ret = 0;
> break;
> case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
> --
> 1.6.2.5
>
>
^ permalink raw reply [flat|nested] 2+ messages in thread
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2010-05-29 20:48 [Qemu-devel] [PATCH] sparc32 SuperSPARC MMU Breakpoint Action register (SS-20 OBP fix) Artyom Tarasenko
2010-05-29 21:27 ` [Qemu-devel] " Blue Swirl
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