From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=44184 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OIr73-0002z6-61 for qemu-devel@nongnu.org; Sun, 30 May 2010 18:36:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OIr6k-0000FL-0q for qemu-devel@nongnu.org; Sun, 30 May 2010 18:35:51 -0400 Received: from fg-out-1718.google.com ([72.14.220.155]:35564) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OIr6j-0000FD-Qw for qemu-devel@nongnu.org; Sun, 30 May 2010 18:35:49 -0400 Received: by fg-out-1718.google.com with SMTP id 16so913741fgg.10 for ; Sun, 30 May 2010 15:35:48 -0700 (PDT) From: Artyom Tarasenko Date: Mon, 31 May 2010 00:35:46 +0200 Message-Id: <1275258946-15739-1-git-send-email-atar4qemu@gmail.com> Subject: [Qemu-devel] [PATCH] sparc32 esp fix spurious interrupts in chip reset List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: blauwirbel@gmail.com, Artyom Tarasenko lower interrupt during chip reset. Otherwise the ESP_RSTAT register may get out of sync with the IRQ line status. This effect became visible after commit 65899fe3 Signed-off-by: Artyom Tarasenko --- hw/esp.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/hw/esp.c b/hw/esp.c index 0a8cf6e..0532c67 100644 --- a/hw/esp.c +++ b/hw/esp.c @@ -423,6 +423,7 @@ static void esp_reset(DeviceState *d) { ESPState *s = container_of(d, ESPState, busdev.qdev); + esp_lower_irq(s); memset(s->rregs, 0, ESP_REGS); memset(s->wregs, 0, ESP_REGS); s->rregs[ESP_TCHI] = TCHI_FAS100A; // Indicate fas100a -- 1.6.2.5