From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=59103 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OKcOD-000624-5D for qemu-devel@nongnu.org; Fri, 04 Jun 2010 15:17:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OKcOB-0002ba-TU for qemu-devel@nongnu.org; Fri, 04 Jun 2010 15:17:08 -0400 Received: from are.twiddle.net ([75.149.56.221]:54804) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OKcOA-0002az-I3 for qemu-devel@nongnu.org; Fri, 04 Jun 2010 15:17:07 -0400 From: Richard Henderson Date: Fri, 4 Jun 2010 12:14:33 -0700 Message-Id: <1275678883-7082-26-git-send-email-rth@twiddle.net> In-Reply-To: <1275678883-7082-1-git-send-email-rth@twiddle.net> References: <1275678883-7082-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 25/35] tcg-s390: Use the MULTIPLY IMMEDIATE instructions. List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: agraf@suse.de, aurelien@aurel32.net Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.c | 43 +++++++++++++++++++++++++++++++++++++++---- 1 files changed, 39 insertions(+), 4 deletions(-) diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c index 5446591..f1e00e9 100644 --- a/tcg/s390/tcg-target.c +++ b/tcg/s390/tcg-target.c @@ -36,6 +36,7 @@ #define TCG_CT_CONST_32 0x0100 #define TCG_CT_CONST_NEG 0x0200 #define TCG_CT_CONST_ADDI 0x0400 +#define TCG_CT_CONST_MULI 0x8000 #define TCG_CT_CONST_ANDI 0x1000 #define TCG_CT_CONST_ORI 0x2000 #define TCG_CT_CONST_XORI 0x4000 @@ -64,6 +65,8 @@ typedef enum S390Opcode { RIL_LGFI = 0xc001, RIL_LLIHF = 0xc00e, RIL_LLILF = 0xc00f, + RIL_MSFI = 0xc201, + RIL_MSGFI = 0xc200, RIL_NIHF = 0xc00a, RIL_NILF = 0xc00b, RIL_OIHF = 0xc00c, @@ -83,6 +86,8 @@ typedef enum S390Opcode { RI_LLIHL = 0xa50d, RI_LLILH = 0xa50e, RI_LLILL = 0xa50f, + RI_MGHI = 0xa70d, + RI_MHI = 0xa70c, RI_NIHH = 0xa504, RI_NIHL = 0xa505, RI_NILH = 0xa506, @@ -336,6 +341,10 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) ct->ct &= ~TCG_CT_REG; ct->ct |= TCG_CT_CONST_ADDI; break; + case 'K': + ct->ct &= ~TCG_CT_REG; + ct->ct |= TCG_CT_CONST_MULI; + break; case 'A': ct->ct &= ~TCG_CT_REG; ct->ct |= TCG_CT_CONST_ANDI; @@ -497,6 +506,16 @@ static int tcg_target_const_match(tcg_target_long val, } else { return val == (int16_t)val; } + } else if (ct & TCG_CT_CONST_MULI) { + /* Immediates that may be used with multiply. If we have the + general-instruction-extensions, then we have MULTIPLY SINGLE + IMMEDIATE with a signed 32-bit, otherwise we have only + MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */ + if (facilities & FACILITY_GEN_INST_EXT) { + return val == (int32_t)val; + } else { + return val == (int16_t)val; + } } else if (ct & TCG_CT_CONST_ANDI) { return tcg_match_andi(ct, val); } else if (ct & TCG_CT_CONST_ORI) { @@ -1511,10 +1530,26 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_mul_i32: - tcg_out_insn(s, RRE, MSR, args[0], args[2]); + if (const_args[2]) { + if ((int32_t)args[2] == (int16_t)args[2]) { + tcg_out_insn(s, RI, MHI, args[0], args[2]); + } else { + tcg_out_insn(s, RIL, MSFI, args[0], args[2]); + } + } else { + tcg_out_insn(s, RRE, MSR, args[0], args[2]); + } break; case INDEX_op_mul_i64: - tcg_out_insn(s, RRE, MSGR, args[0], args[2]); + if (const_args[2]) { + if (args[2] == (int16_t)args[2]) { + tcg_out_insn(s, RI, MGHI, args[0], args[2]); + } else { + tcg_out_insn(s, RIL, MSGFI, args[0], args[2]); + } + } else { + tcg_out_insn(s, RRE, MSGR, args[0], args[2]); + } break; case INDEX_op_div2_i32: @@ -1755,7 +1790,7 @@ static const TCGTargetOpDef s390_op_defs[] = { { INDEX_op_add_i32, { "r", "0", "rWI" } }, { INDEX_op_sub_i32, { "r", "0", "rWNI" } }, - { INDEX_op_mul_i32, { "r", "0", "r" } }, + { INDEX_op_mul_i32, { "r", "0", "rK" } }, { INDEX_op_div2_i32, { "b", "a", "0", "1", "r" } }, { INDEX_op_divu2_i32, { "b", "a", "0", "1", "r" } }, @@ -1817,7 +1852,7 @@ static const TCGTargetOpDef s390_op_defs[] = { { INDEX_op_add_i64, { "r", "0", "rI" } }, { INDEX_op_sub_i64, { "r", "0", "rNI" } }, - { INDEX_op_mul_i64, { "r", "0", "r" } }, + { INDEX_op_mul_i64, { "r", "0", "rK" } }, { INDEX_op_div2_i64, { "b", "a", "0", "1", "r" } }, { INDEX_op_divu2_i64, { "b", "a", "0", "1", "r" } }, -- 1.7.0.1