From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=39312 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OQleX-0001v2-B4 for qemu-devel@nongnu.org; Mon, 21 Jun 2010 14:23:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OQleV-0000C6-T1 for qemu-devel@nongnu.org; Mon, 21 Jun 2010 14:23:25 -0400 Received: from fg-out-1718.google.com ([72.14.220.152]:9644) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OQleV-0000Bo-Oo for qemu-devel@nongnu.org; Mon, 21 Jun 2010 14:23:23 -0400 Received: by fg-out-1718.google.com with SMTP id l26so905893fgb.10 for ; Mon, 21 Jun 2010 11:23:22 -0700 (PDT) From: Artyom Tarasenko Date: Mon, 21 Jun 2010 20:23:21 +0200 Message-Id: <1277144601-30098-1-git-send-email-atar4qemu@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH] [sparc32] mask all interrupts when MASTER_DISABLE is set List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: blauwirbel@gmail.com, Artyom Tarasenko The MASTER_DISABLE bit (aka mask-all) masks all the interrupts. According to Sun-4M System Architecture "The level–15 interrupt sources [...] are maskable with the Interrupt Target Mask Register. While these interrupts are considered ’non–maskable’ within the SPARC IU, a mask capability is provided to allow the boot firmware to establish a basic environment before receiving any level–15 interrupts, which are non–maskable within SPARC. A mask–all bit is provided to allow disabling of all external interrupts during change of the CIT." Signed-off-by: Artyom Tarasenko --- hw/slavio_intctl.c | 9 ++++++--- 1 files changed, 6 insertions(+), 3 deletions(-) diff --git a/hw/slavio_intctl.c b/hw/slavio_intctl.c index b76d3ac..8a38f67 100644 --- a/hw/slavio_intctl.c +++ b/hw/slavio_intctl.c @@ -289,9 +289,12 @@ static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs) } } - /* Level 15 and CPU timer interrupts are not maskable */ - pil_pending |= s->slaves[i].intreg_pending & - (CPU_IRQ_INT15_IN | CPU_IRQ_TIMER_IN); + /* Level 15 and CPU timer interrupts are only masked when + the MASTER_DISABLE bit is set */ + if (!(s->intregm_disabled & MASTER_DISABLE)) { + pil_pending |= s->slaves[i].intreg_pending & + (CPU_IRQ_INT15_IN | CPU_IRQ_TIMER_IN); + } /* Add soft interrupts */ pil_pending |= (s->slaves[i].intreg_pending & CPU_SOFTIRQ_MASK) >> 16; -- 1.6.2.5