From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=37447 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OX7CF-0000LC-88 for qemu-devel@nongnu.org; Fri, 09 Jul 2010 02:36:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OX7CD-00047v-CQ for qemu-devel@nongnu.org; Fri, 09 Jul 2010 02:36:26 -0400 Received: from mail-pz0-f45.google.com ([209.85.210.45]:56009) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OX7CD-00047e-7s for qemu-devel@nongnu.org; Fri, 09 Jul 2010 02:36:25 -0400 Received: by pzk10 with SMTP id 10so411050pzk.4 for ; Thu, 08 Jul 2010 23:36:24 -0700 (PDT) From: Alexandre Courbot Date: Fri, 9 Jul 2010 15:38:35 +0900 Message-Id: <1278657516-26130-2-git-send-email-gnurou@gmail.com> In-Reply-To: <1278657516-26130-1-git-send-email-gnurou@gmail.com> References: <1278657516-26130-1-git-send-email-gnurou@gmail.com> Subject: [Qemu-devel] [PATCH 1/2] target-sh4: Split the LDST macro into 2 sub-macros List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Alexandre Courbot The LDST macro is used to generate ldc and stc instructions that work with a specific register. However, the SGR register only supports stc up to SH4A, which supports both stc and ldc. This patch creates two sub-macros named LD and ST that handle generating ldc and stc instructions separately, and redeclares LDST to use these sub-macro. --- target-sh4/translate.c | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-) diff --git a/target-sh4/translate.c b/target-sh4/translate.c index d0d6c00..3abafd0 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -1511,7 +1511,7 @@ static void _decode_opc(DisasContext * ctx) tcg_temp_free(addr); } return; -#define LDST(reg,ldnum,ldpnum,stnum,stpnum,prechk) \ +#define LD(reg,ldnum,ldpnum,prechk) \ case ldnum: \ prechk \ tcg_gen_mov_i32 (cpu_##reg, REG(B11_8)); \ @@ -1520,7 +1520,8 @@ static void _decode_opc(DisasContext * ctx) prechk \ tcg_gen_qemu_ld32s (cpu_##reg, REG(B11_8), ctx->memidx); \ tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); \ - return; \ + return; +#define ST(reg,stnum,stpnum,prechk) \ case stnum: \ prechk \ tcg_gen_mov_i32 (REG(B11_8), cpu_##reg); \ @@ -1535,6 +1536,9 @@ static void _decode_opc(DisasContext * ctx) tcg_temp_free(addr); \ } \ return; +#define LDST(reg,ldnum,ldpnum,stnum,stpnum,prechk) \ + LD(reg,ldnum,ldpnum,prechk) \ + ST(reg,stnum,stpnum,prechk) LDST(gbr, 0x401e, 0x4017, 0x0012, 0x4013, {}) LDST(vbr, 0x402e, 0x4027, 0x0022, 0x4023, CHECK_PRIVILEGED) LDST(ssr, 0x403e, 0x4037, 0x0032, 0x4033, CHECK_PRIVILEGED) -- 1.7.1.1