[Qemu-devel] [PATCH v2 0/2] target-sh4: Add support for missing ldc & stc instructions with sgr

[Qemu-devel] [PATCH v2 0/2] target-sh4: Add support for missing ldc & stc instructions with sgr

[Alexandre Courbot]

This series of patch adds support for the missing ldc & stc privileged
instructions with the sgr register. In order to take the difference
of support between SH4A and SH4 (which does not recognize ldc with sgr),
the LDST macro has been split into two simpler macros.

Changelog from v1: signed off the patches (sorry for omitting it).

[Qemu-devel] [PATCH v2 1/2] target-sh4: Split the LDST macro into 2 sub-macros

[Alexandre Courbot]

The LDST macro is used to generate ldc and stc instructions that work with a
specific register. However, the SGR register only supports stc up to SH4A,
which supports both stc and ldc. This patch creates two sub-macros named LD
and ST that handle generating ldc and stc instructions separately, and
redeclares LDST to use these sub-macro.

Signed-off-by: Alexandre Courbot <gnurou@gmail.com>
---
 target-sh4/translate.c |    8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index d0d6c00..3abafd0 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -1511,7 +1511,7 @@ static void _decode_opc(DisasContext * ctx)
 	    tcg_temp_free(addr);
 	}
 	return;
-#define LDST(reg,ldnum,ldpnum,stnum,stpnum,prechk)		\
+#define LD(reg,ldnum,ldpnum,prechk)		\
   case ldnum:							\
     prechk    							\
     tcg_gen_mov_i32 (cpu_##reg, REG(B11_8));			\
@@ -1520,7 +1520,8 @@ static void _decode_opc(DisasContext * ctx)
     prechk    							\
     tcg_gen_qemu_ld32s (cpu_##reg, REG(B11_8), ctx->memidx);	\
     tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);		\
-    return;							\
+    return;
+#define ST(reg,stnum,stpnum,prechk)		\
   case stnum:							\
     prechk    							\
     tcg_gen_mov_i32 (REG(B11_8), cpu_##reg);			\
@@ -1535,6 +1536,9 @@ static void _decode_opc(DisasContext * ctx)
 	tcg_temp_free(addr);					\
     }								\
     return;
+#define LDST(reg,ldnum,ldpnum,stnum,stpnum,prechk)		\
+	LD(reg,ldnum,ldpnum,prechk)				\
+	ST(reg,stnum,stpnum,prechk)
 	LDST(gbr,  0x401e, 0x4017, 0x0012, 0x4013, {})
 	LDST(vbr,  0x402e, 0x4027, 0x0022, 0x4023, CHECK_PRIVILEGED)
 	LDST(ssr,  0x403e, 0x4037, 0x0032, 0x4033, CHECK_PRIVILEGED)
-- 
1.7.1.1

[Qemu-devel] [PATCH v2 2/2] target-sh4: Add support for ldc & stc with sgr

[Alexandre Courbot]

Add support for the following missing priviledged intructions:

For SH4:
- stc sgr, Rn
- stc.l sgr, @-Rn

For SH4A:
- ldc Rm, sgr
- ldc.l @Rm+, sgr

Signed-off-by: Alexandre Courbot <gnurou@gmail.com>
---
 target-sh4/translate.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 3abafd0..deee939 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -1543,6 +1543,8 @@ static void _decode_opc(DisasContext * ctx)
 	LDST(vbr,  0x402e, 0x4027, 0x0022, 0x4023, CHECK_PRIVILEGED)
 	LDST(ssr,  0x403e, 0x4037, 0x0032, 0x4033, CHECK_PRIVILEGED)
 	LDST(spc,  0x404e, 0x4047, 0x0042, 0x4043, CHECK_PRIVILEGED)
+	ST(sgr,  0x003a, 0x4032, CHECK_PRIVILEGED)
+	LD(sgr,  0x403a, 0x4036, CHECK_PRIVILEGED if (!(ctx->features & SH_FEATURE_SH4A)) break;)
 	LDST(dbr,  0x40fa, 0x40f6, 0x00fa, 0x40f2, CHECK_PRIVILEGED)
 	LDST(mach, 0x400a, 0x4006, 0x000a, 0x4002, {})
 	LDST(macl, 0x401a, 0x4016, 0x001a, 0x4012, {})
-- 
1.7.1.1

Re: [Qemu-devel] [PATCH v2 0/2] target-sh4: Add support for missing ldc & stc instructions with sgr

[Aurelien Jarno]

On Mon, Jul 12, 2010 at 02:05:30PM +0900, Alexandre Courbot wrote:
> This series of patch adds support for the missing ldc & stc privileged
> instructions with the sgr register. In order to take the difference
> of support between SH4A and SH4 (which does not recognize ldc with sgr),
> the LDST macro has been split into two simpler macros.
> 
> Changelog from v1: signed off the patches (sorry for omitting it).
> 

Thanks, both applied.

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net