From: Richard Henderson <richard.henderson@linaro.org>
To: Alexey Baturo <baturo.alexey@gmail.com>
Cc: zhiwei_liu@linux.alibaba.com, palmer@dabbelt.com,
Alistair.Francis@wdc.com, sagark@eecs.berkeley.edu,
kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org,
qemu-riscv@nongnu.org
Subject: Re: [PATCH v2 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking
Date: Fri, 29 Dec 2023 10:35:15 +1100 [thread overview]
Message-ID: <127b5fc3-b852-4d5c-b53b-1fafcf22cd1f@linaro.org> (raw)
In-Reply-To: <20231224044812.2072140-4-me@deliversmonkey.space>
On 12/24/23 15:48, Alexey Baturo wrote:
> From: Alexey Baturo <baturo.alexey@gmail.com>
>
> Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
> ---
> target/riscv/cpu.h | 4 +++
> target/riscv/cpu_helper.c | 54 +++++++++++++++++++++++++++++++++++++++
> 2 files changed, 58 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index bd379ee653..c607a94bba 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -672,6 +672,10 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
> void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
> uint64_t *cs_base, uint32_t *pflags);
>
> +bool riscv_cpu_bare_mode(CPURISCVState *env);
> +RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env);
> +int riscv_pm_get_pmlen(RISCVPmPmm pmm);
> +
> RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
> target_ulong *ret_value,
> target_ulong new_value, target_ulong write_mask);
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index a3d477d226..47f325294e 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -139,6 +139,60 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
> *pflags = flags;
> }
>
> +RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env)
> +{
> +#ifndef CONFIG_USER_ONLY
> + int priv_mode = cpu_address_mode(env);
> + int pmm = 0;
> + /* Get current PMM field */
> + switch (priv_mode) {
> + case PRV_M:
> + pmm = riscv_cpu_cfg(env)->ext_smmpm ?
> + get_field(env->mseccfg, MSECCFG_PMM) : PMM_FIELD_DISABLED;
> + break;
> + case PRV_S:
> + pmm = riscv_cpu_cfg(env)->ext_smnpm ?
> + get_field(env->menvcfg, MENVCFG_PMM) : PMM_FIELD_DISABLED;
> + break;
> + case PRV_U:
> + pmm = riscv_cpu_cfg(env)->ext_ssnpm ?
> + get_field(env->senvcfg, SENVCFG_PMM) : PMM_FIELD_DISABLED;
> + break;
> + default:
> + g_assert_not_reached();
> + }
> + return pmm;
> +#endif
> +}
> +
> +bool riscv_cpu_bare_mode(CPURISCVState *env)
> +{
> +#ifndef CONFIG_USER_ONLY
> + int satp_mode = 0;
> + if (riscv_cpu_mxl(env) == MXL_RV32) {
> + satp_mode = get_field(env->satp, SATP32_MODE);
> + } else {
> + satp_mode = get_field(env->satp, SATP64_MODE);
> + }
> + return (satp_mode == VM_1_10_MBARE);
> +#endif
> +}
You can't leave these with no return statement for CONFIG_USER_ONLY.
You probably don't need the ifdef at all, come to that.
r~
next prev parent reply other threads:[~2023-12-28 23:35 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-24 4:48 [PATCH v2 0/6] Pointer Masking update for Zjpm v0.8 Alexey Baturo
2023-12-24 4:48 ` [PATCH v2 1/6] target/riscv: Remove obsolete pointer masking extension code Alexey Baturo
2023-12-24 4:48 ` [PATCH v2 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8 Alexey Baturo
2023-12-24 4:48 ` [PATCH v2 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking Alexey Baturo
2023-12-28 23:35 ` Richard Henderson [this message]
2023-12-24 4:48 ` [PATCH v2 4/6] target/riscv: Add pointer masking tb flags Alexey Baturo
2023-12-28 23:33 ` Richard Henderson
2023-12-29 16:53 ` Alexey Baturo
2023-12-24 4:48 ` [PATCH v2 5/6] target/riscv: Update address modify functions to take into account pointer masking Alexey Baturo
2023-12-28 23:46 ` Richard Henderson
2023-12-24 4:48 ` [PATCH v2 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension Alexey Baturo
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