* Re: [Qemu-devel] [PATCH] Ignore writes of perf reg (cp15 with crm == 12)
2010-07-28 14:23 ` [Qemu-devel] " Loïc Minier
@ 2010-07-30 21:30 ` Aurelien Jarno
0 siblings, 0 replies; 4+ messages in thread
From: Aurelien Jarno @ 2010-07-30 21:30 UTC (permalink / raw)
To: Loïc Minier; +Cc: qemu-devel
On Wed, Jul 28, 2010 at 04:23:05PM +0200, Loïc Minier wrote:
> I found out Matt Waddel has written a better looking patch, but I
> didn't test it; reviews welcome -- attached
>
> --
> Loïc Minier
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Date: Tue, 27 Jul 2010 11:22:12 -0600
From: Matt Waddel <matt.waddel@canonical.com>
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To: =?ISO-8859-1?Q?Lo=EFc_Minier?= <loic.minier@linaro.org>
Subject: qemu cp15 register patch
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>
>
The patch needs a Signed-off-by.
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 7440163..b5d8a6c 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -130,6 +130,7 @@ typedef struct CPUARMState {
> uint32_t c6_data;
> uint32_t c9_insn; /* Cache lockdown registers. */
> uint32_t c9_data;
> + uint32_t c9_pmcr_data; /* Performance Monitor Control Register */
The name looks a bit strange, c9_pmcr seems to be better.
> uint32_t c12_vbar; /* secure/nonsecure vector base address register. */
> uint32_t c12_mvbar; /* monitor vector base address register. */
> uint32_t c13_fcse; /* FCSE PID. */
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 1f5f307..2136c07 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -1558,6 +1558,15 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
> case 1: /* TCM memory region registers. */
> /* Not implemented. */
> goto bad_reg;
> + case 12:
> + switch (op2) {
> + case 0:
> + env->cp15.c9_pmcr_data = val;
Maybe writing a small comment that it is not fully implemented will help
for later.
> + break;
> + default:
> + goto bad_reg;
> + }
> + break;
> default:
> goto bad_reg;
> }
> @@ -1897,6 +1906,13 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
> goto bad_reg;
> /* L2 Lockdown and Auxiliary control. */
> return 0;
> + case 12:
> + switch (op2) {
> + case 0:
> + return env->cp15.c9_pmcr_data;
> + default:
> + goto bad_reg;
> + }
> default:
> goto bad_reg;
> }
> diff --git a/target-arm/machine.c b/target-arm/machine.c
> index 8595549..026776d 100644
> --- a/target-arm/machine.c
> +++ b/target-arm/machine.c
> @@ -46,6 +46,7 @@ void cpu_save(QEMUFile *f, void *opaque)
> qemu_put_be32(f, env->cp15.c6_data);
> qemu_put_be32(f, env->cp15.c9_insn);
> qemu_put_be32(f, env->cp15.c9_data);
> + qemu_put_be32(f, env->cp15.c9_pmcr_data);
> qemu_put_be32(f, env->cp15.c13_fcse);
> qemu_put_be32(f, env->cp15.c13_context);
> qemu_put_be32(f, env->cp15.c13_tls1);
> @@ -156,6 +157,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
> env->cp15.c6_data = qemu_get_be32(f);
> env->cp15.c9_insn = qemu_get_be32(f);
> env->cp15.c9_data = qemu_get_be32(f);
> + env->cp15.c9_pmcr_data = qemu_get_be32(f);
> env->cp15.c13_fcse = qemu_get_be32(f);
> env->cp15.c13_context = qemu_get_be32(f);
> env->cp15.c13_tls1 = qemu_get_be32(f);
>
Adding fields here imply a change of CPU_SAVE_VERSION.
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
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