From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1HgclW-0001jY-NZ for qemu-devel@nongnu.org; Wed, 25 Apr 2007 04:22:18 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1HgclV-0001jM-6O for qemu-devel@nongnu.org; Wed, 25 Apr 2007 04:22:18 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1HgclU-0001jJ-Qx for qemu-devel@nongnu.org; Wed, 25 Apr 2007 04:22:16 -0400 Received: from wr-out-0506.google.com ([64.233.184.228]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Hgcfs-0008Ov-Tx for qemu-devel@nongnu.org; Wed, 25 Apr 2007 04:16:29 -0400 Received: by wr-out-0506.google.com with SMTP id i20so235095wra for ; Wed, 25 Apr 2007 01:16:28 -0700 (PDT) Message-ID: <12835c8f0704250116i15a82885j7f6311715ad4374b@mail.gmail.com> Date: Wed, 25 Apr 2007 01:16:27 -0700 From: "Shashidhar Mysore" MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_Part_153727_5730972.1177488987413" Subject: [Qemu-devel] Minos-type integrity checking in QEMU Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org ------=_Part_153727_5730972.1177488987413 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Content-Disposition: inline Hi, I am trying to incorporate into QEMU (x86) some structures to maintain integrity of data that flows in the processor. Specifically, I want to maintain a bit for every physical memory address and transfer the state information for every address along onto the virtual memory, and also down to the instructions which operate on data, and bit arrays for registers (so that when an operand is fetched from a particular register, we also have the state information for that register). I am trying to build a Minos type architecture ( http://minos.cs.ucdavis.edu/) but in QEMU instead of Bochs. For this, as far as I can see, I need to maintain a set of new structures to shadow the physical memory and make changes to the micro ops defined in target-i386/op.c so that every instruction can track the state and store them for every register used as an operand. I'm not sure if somebody has already implemented such a system on QEMU? I am just beginning to think and work on this, so any pointers/suggestions would be greatly appreciated. Please let me know your views on this. Thanks, -Shashi. ------=_Part_153727_5730972.1177488987413 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline Hi,

I am trying to incorporate into QEMU (x86) some structures to maintain integrity of data that flows in the processor. Specifically, I want to maintain a bit for every physical memory address and transfer the state information for every address along onto the virtual memory, and also down to the instructions which operate on data, and bit arrays for registers (so that when an operand is fetched from a particular register, we also have the state information for that register). I am trying to build a Minos type architecture ( http://minos.cs.ucdavis.edu/) but in QEMU instead of Bochs.

For this, as far as I can see, I need to maintain a set of new structures to shadow the physical memory and make changes to the micro ops defined in target-i386/op.c so that every instruction can track the state and store them for every register used as an operand. I'm not sure if somebody has already implemented such a system on QEMU? I am just beginning to think and work on this, so any pointers/suggestions would be greatly appreciated. Please let me know your views on this.

Thanks,
-Shashi.
------=_Part_153727_5730972.1177488987413--