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From: Huang Ying <ying.huang@intel.com>
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Date: Fri, 08 Oct 2010 10:50:59 +0800
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Subject: [Qemu-devel] Re: [patch uq/master 7/8] MCE: Relay UCR MCE to guest
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To: Marcelo Tosatti <mtosatti@redhat.com>
Cc: Dean Nelson <dnelson@redhat.com>, Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>, "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>, "kvm@vger.kernel.org" <kvm@vger.kernel.org>

On Thu, 2010-10-07 at 00:05 +0800, Marcelo Tosatti wrote:
> On Wed, Oct 06, 2010 at 10:58:36AM +0900, Hidetoshi Seto wrote:
> > I got some more question:
> > 
> > (2010/10/05 3:54), Marcelo Tosatti wrote:
> > > Index: qemu/target-i386/cpu.h
> > > ===================================================================
> > > --- qemu.orig/target-i386/cpu.h
> > > +++ qemu/target-i386/cpu.h
> > > @@ -250,16 +250,32 @@
> > >  #define PG_ERROR_RSVD_MASK 0x08
> > >  #define PG_ERROR_I_D_MASK  0x10
> > >  
> > > -#define MCG_CTL_P	(1UL<<8)   /* MCG_CAP register available */
> > > +#define MCG_CTL_P	(1ULL<<8)   /* MCG_CAP register available */
> > > +#define MCG_SER_P	(1ULL<<24) /* MCA recovery/new status bits */
> > >  
> > > -#define MCE_CAP_DEF	MCG_CTL_P
> > > +#define MCE_CAP_DEF	(MCG_CTL_P|MCG_SER_P)
> > >  #define MCE_BANKS_DEF	10
> > >  
> > 
> > It seems that current kvm doesn't support SER_P, so injecting SRAO
> > to guest will mean that guest receives VAL|UC|!PCC and RIPV event
> > from virtual processor that doesn't have SER_P.
> 
> Dean also noted this. I don't think it was deliberate choice to not
> expose SER_P. Huang?

In fact, that should be a BUG. I will fix it as soon as possible.

Best Regards,
Huang Ying