From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=43183 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1P9Hu4-0002Gk-Mu for qemu-devel@nongnu.org; Fri, 22 Oct 2010 09:43:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1P9Hu3-0003DQ-Ed for qemu-devel@nongnu.org; Fri, 22 Oct 2010 09:43:28 -0400 Received: from mx1.redhat.com ([209.132.183.28]:45845) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1P9Hu3-0003DA-8A for qemu-devel@nongnu.org; Fri, 22 Oct 2010 09:43:27 -0400 From: Kevin Wolf Date: Fri, 22 Oct 2010 15:43:49 +0200 Message-Id: <1287755036-27688-5-git-send-email-kwolf@redhat.com> In-Reply-To: <1287755036-27688-1-git-send-email-kwolf@redhat.com> References: <1287755036-27688-1-git-send-email-kwolf@redhat.com> Subject: [Qemu-devel] [PATCH 04/11] ide: set WCACHE supported in IDENTIFY data List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: anthony@codemonkey.ws Cc: kwolf@redhat.com, qemu-devel@nongnu.org From: Christoph Hellwig ATA does not only have the WCACHE enabled bit in identify word 85, but also a WCACHE supported bit in word 82. While the Linux kernel is fine with the latter at least hdparm also needs the former before correctly displaying the cache settings. There's also a non-zero chance other operating systems are more picky in their volatile write cache detection. Signed-off-by: Christoph Hellwig Signed-off-by: Kevin Wolf --- hw/ide/core.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/ide/core.c b/hw/ide/core.c index 06b6e14..5ccb09c 100644 --- a/hw/ide/core.c +++ b/hw/ide/core.c @@ -146,8 +146,8 @@ static void ide_identify(IDEState *s) put_le16(p + 68, 120); put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */ put_le16(p + 81, 0x16); /* conforms to ata5 */ - /* 14=NOP supported, 0=SMART supported */ - put_le16(p + 82, (1 << 14) | 1); + /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */ + put_le16(p + 82, (1 << 14) | (1 << 5) | 1); /* 13=flush_cache_ext,12=flush_cache,10=lba48 */ put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10)); /* 14=set to 1, 1=SMART self test, 0=SMART error logging */ -- 1.7.2.3