From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=37336 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PGbod-0005Rb-1T for qemu-devel@nongnu.org; Thu, 11 Nov 2010 13:24:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PGboa-0000f2-TM for qemu-devel@nongnu.org; Thu, 11 Nov 2010 13:24:06 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:46366) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PGboa-0000eA-FY for qemu-devel@nongnu.org; Thu, 11 Nov 2010 13:24:04 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.69) (envelope-from ) id 1PGboY-0007VI-Sv for qemu-devel@nongnu.org; Thu, 11 Nov 2010 18:24:02 +0000 From: Peter Maydell Date: Thu, 11 Nov 2010 18:23:56 +0000 Message-Id: <1289499842-28818-3-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1289499842-28818-1-git-send-email-peter.maydell@linaro.org> References: <1289499842-28818-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 2/8] ARM: Fix decoding of Neon forms of VCVT between float and fixed point List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Fix errors in the decoding of the Neon forms of fixed-point VCVT: * fixed-point VCVT is op 14 and 15, not 15 and 16 * the fbits immediate field was being misinterpreted * the sense of the to_fixed bit was inverted Signed-off-by: Peter Maydell --- target-arm/translate.c | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 0c8439a..696abf6 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -4850,11 +4850,15 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) } neon_store_reg64(cpu_V0, rd + pass); } - } else if (op == 15 || op == 16) { + } else if (op >= 14) { /* VCVT fixed-point. */ + /* We have already masked out the must-be-1 top bit of imm6, + * hence this 32-shift where the ARM ARM has 64-imm6. + */ + shift = 32 - shift; for (pass = 0; pass < (q ? 4 : 2); pass++) { tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, pass)); - if (op & 1) { + if (!(op & 1)) { if (u) gen_vfp_ulto(0, shift); else -- 1.7.1