From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=37370 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PGboe-0005Si-Si for qemu-devel@nongnu.org; Thu, 11 Nov 2010 13:24:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PGboa-0000eu-TF for qemu-devel@nongnu.org; Thu, 11 Nov 2010 13:24:08 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:46370) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PGboa-0000e8-FT for qemu-devel@nongnu.org; Thu, 11 Nov 2010 13:24:04 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.69) (envelope-from ) id 1PGboY-0007VO-UX for qemu-devel@nongnu.org; Thu, 11 Nov 2010 18:24:02 +0000 From: Peter Maydell Date: Thu, 11 Nov 2010 18:23:59 +0000 Message-Id: <1289499842-28818-6-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1289499842-28818-1-git-send-email-peter.maydell@linaro.org> References: <1289499842-28818-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 5/8] ARM: Return correct result for single<->double conversion of NaN List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org The ARM ARM defines that if the input to a single<->double conversion is a NaN then the output is always forced to be a quiet NaN by setting the most significant bit of the fraction part. Signed-off-by: Peter Maydell --- target-arm/helper.c | 20 ++++++++++++++++++-- 1 files changed, 18 insertions(+), 2 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 72ba314..628094f 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2529,12 +2529,28 @@ float32 VFP_HELPER(tosiz, d)(float64 x, CPUState *env) /* floating point conversion */ float64 VFP_HELPER(fcvtd, s)(float32 x, CPUState *env) { - return float32_to_float64(x, &env->vfp.fp_status); + float64 r = float32_to_float64(x, &env->vfp.fp_status); + /* ARM requires that S<->D conversion of any kind of NaN generates + * a quiet NaN by forcing the most significant frac bit to 1. + */ + if (float64_is_signaling_nan(r)) + { + return make_float64(float64_val(r) | (1LL << 51)); + } + return r; } float32 VFP_HELPER(fcvts, d)(float64 x, CPUState *env) { - return float64_to_float32(x, &env->vfp.fp_status); + float32 r = float64_to_float32(x, &env->vfp.fp_status); + /* ARM requires that S<->D conversion of any kind of NaN generates + * a quiet NaN by forcing the most significant frac bit to 1. + */ + if (float32_is_signaling_nan(r)) + { + return make_float32(float32_val(r) | (1 << 22)); + } + return r; } /* VFP3 fixed point conversion. */ -- 1.7.1