* [Qemu-devel] [PATCH 01/10] ide: split ide command interpretation off
2010-11-17 1:05 [Qemu-devel] [PATCH 00/10] AHCI emulation support Alexander Graf
@ 2010-11-17 1:05 ` Alexander Graf
2010-11-17 1:05 ` [Qemu-devel] [PATCH 02/10] ide: fix whitespace gap in ide_exec_cmd Alexander Graf
` (8 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Alexander Graf @ 2010-11-17 1:05 UTC (permalink / raw)
To: QEMU-devel Developers; +Cc: tj, Joerg Roedel, Sebastian Herbszt, Roland Elek
The ATA command interpretation code can be used for PATA and SATA
interfaces alike. So let's split it out into a separate function.
Signed-off-by: Alexander Graf <agraf@suse.de>
---
hw/ide/core.c | 20 ++++++++++++++------
hw/ide/internal.h | 2 ++
2 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/hw/ide/core.c b/hw/ide/core.c
index 484e0ca..ee551ac 100644
--- a/hw/ide/core.c
+++ b/hw/ide/core.c
@@ -1790,9 +1790,6 @@ static void ide_clear_hob(IDEBus *bus)
void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
IDEBus *bus = opaque;
- IDEState *s;
- int n;
- int lba48 = 0;
#ifdef DEBUG_IDE
printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
@@ -1853,17 +1850,29 @@ void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
default:
case 7:
/* command */
+ ide_exec_cmd(opaque, val);
+ break;
+ }
+}
+
+
+void ide_exec_cmd(IDEBus *bus, uint32_t val)
+{
+ IDEState *s;
+ int n;
+ int lba48 = 0;
+
#if defined(DEBUG_IDE)
printf("ide: CMD=%02x\n", val);
#endif
s = idebus_active_if(bus);
/* ignore commands to non existant slave */
if (s != bus->ifs && !s->bs)
- break;
+ return;
/* Only DEVICE RESET is allowed while BSY or/and DRQ are set */
if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET)
- break;
+ return;
switch(val) {
case WIN_IDENTIFY:
@@ -2354,7 +2363,6 @@ void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
ide_set_irq(s->bus);
break;
}
- }
}
uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
diff --git a/hw/ide/internal.h b/hw/ide/internal.h
index d652e06..e7e1f80 100644
--- a/hw/ide/internal.h
+++ b/hw/ide/internal.h
@@ -564,6 +564,8 @@ void ide_init2_with_non_qdev_drives(IDEBus *bus, DriveInfo *hd0,
DriveInfo *hd1, qemu_irq irq);
void ide_init_ioport(IDEBus *bus, int iobase, int iobase2);
+void ide_exec_cmd(IDEBus *bus, uint32_t val);
+
/* hw/ide/qdev.c */
void ide_bus_new(IDEBus *idebus, DeviceState *dev);
IDEDevice *ide_create_drive(IDEBus *bus, int unit, DriveInfo *drive);
--
1.6.0.2
^ permalink raw reply related [flat|nested] 18+ messages in thread* [Qemu-devel] [PATCH 02/10] ide: fix whitespace gap in ide_exec_cmd
2010-11-17 1:05 [Qemu-devel] [PATCH 00/10] AHCI emulation support Alexander Graf
2010-11-17 1:05 ` [Qemu-devel] [PATCH 01/10] ide: split ide command interpretation off Alexander Graf
@ 2010-11-17 1:05 ` Alexander Graf
2010-11-17 1:05 ` [Qemu-devel] [PATCH 03/10] ide: add support for ide extenders Alexander Graf
` (7 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Alexander Graf @ 2010-11-17 1:05 UTC (permalink / raw)
To: QEMU-devel Developers; +Cc: tj, Joerg Roedel, Sebastian Herbszt, Roland Elek
Now that we have the function split out, we have to reindent it.
In order to increase the readability of the actual functional change,
this is split out.
Signed-off-by: Alexander Graf <agraf@suse.de>
---
hw/ide/core.c | 734 ++++++++++++++++++++++++++++----------------------------
1 files changed, 367 insertions(+), 367 deletions(-)
diff --git a/hw/ide/core.c b/hw/ide/core.c
index ee551ac..1849069 100644
--- a/hw/ide/core.c
+++ b/hw/ide/core.c
@@ -1863,423 +1863,423 @@ void ide_exec_cmd(IDEBus *bus, uint32_t val)
int lba48 = 0;
#if defined(DEBUG_IDE)
- printf("ide: CMD=%02x\n", val);
+ printf("ide: CMD=%02x\n", val);
#endif
- s = idebus_active_if(bus);
- /* ignore commands to non existant slave */
- if (s != bus->ifs && !s->bs)
- return;
+ s = idebus_active_if(bus);
+ /* ignore commands to non existant slave */
+ if (s != bus->ifs && !s->bs)
+ return;
- /* Only DEVICE RESET is allowed while BSY or/and DRQ are set */
- if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET)
- return;
+ /* Only DEVICE RESET is allowed while BSY or/and DRQ are set */
+ if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET)
+ return;
- switch(val) {
- case WIN_IDENTIFY:
- if (s->bs && s->drive_kind != IDE_CD) {
- if (s->drive_kind != IDE_CFATA)
- ide_identify(s);
- else
- ide_cfata_identify(s);
- s->status = READY_STAT | SEEK_STAT;
- ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
- } else {
- if (s->drive_kind == IDE_CD) {
- ide_set_signature(s);
- }
- ide_abort_command(s);
- }
- ide_set_irq(s->bus);
- break;
- case WIN_SPECIFY:
- case WIN_RECAL:
- s->error = 0;
+ switch(val) {
+ case WIN_IDENTIFY:
+ if (s->bs && s->drive_kind != IDE_CD) {
+ if (s->drive_kind != IDE_CFATA)
+ ide_identify(s);
+ else
+ ide_cfata_identify(s);
s->status = READY_STAT | SEEK_STAT;
- ide_set_irq(s->bus);
- break;
- case WIN_SETMULT:
- if (s->drive_kind == IDE_CFATA && s->nsector == 0) {
- /* Disable Read and Write Multiple */
- s->mult_sectors = 0;
- s->status = READY_STAT | SEEK_STAT;
- } else if ((s->nsector & 0xff) != 0 &&
- ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
- (s->nsector & (s->nsector - 1)) != 0)) {
- ide_abort_command(s);
- } else {
- s->mult_sectors = s->nsector & 0xff;
- s->status = READY_STAT | SEEK_STAT;
+ ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
+ } else {
+ if (s->drive_kind == IDE_CD) {
+ ide_set_signature(s);
}
- ide_set_irq(s->bus);
- break;
- case WIN_VERIFY_EXT:
- lba48 = 1;
- case WIN_VERIFY:
- case WIN_VERIFY_ONCE:
- /* do sector number check ? */
- ide_cmd_lba48_transform(s, lba48);
+ ide_abort_command(s);
+ }
+ ide_set_irq(s->bus);
+ break;
+ case WIN_SPECIFY:
+ case WIN_RECAL:
+ s->error = 0;
+ s->status = READY_STAT | SEEK_STAT;
+ ide_set_irq(s->bus);
+ break;
+ case WIN_SETMULT:
+ if (s->drive_kind == IDE_CFATA && s->nsector == 0) {
+ /* Disable Read and Write Multiple */
+ s->mult_sectors = 0;
s->status = READY_STAT | SEEK_STAT;
- ide_set_irq(s->bus);
- break;
+ } else if ((s->nsector & 0xff) != 0 &&
+ ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
+ (s->nsector & (s->nsector - 1)) != 0)) {
+ ide_abort_command(s);
+ } else {
+ s->mult_sectors = s->nsector & 0xff;
+ s->status = READY_STAT | SEEK_STAT;
+ }
+ ide_set_irq(s->bus);
+ break;
+ case WIN_VERIFY_EXT:
+ lba48 = 1;
+ case WIN_VERIFY:
+ case WIN_VERIFY_ONCE:
+ /* do sector number check ? */
+ ide_cmd_lba48_transform(s, lba48);
+ s->status = READY_STAT | SEEK_STAT;
+ ide_set_irq(s->bus);
+ break;
case WIN_READ_EXT:
- lba48 = 1;
- case WIN_READ:
- case WIN_READ_ONCE:
- if (!s->bs)
- goto abort_cmd;
- ide_cmd_lba48_transform(s, lba48);
- s->req_nb_sectors = 1;
- ide_sector_read(s);
- break;
+ lba48 = 1;
+ case WIN_READ:
+ case WIN_READ_ONCE:
+ if (!s->bs)
+ goto abort_cmd;
+ ide_cmd_lba48_transform(s, lba48);
+ s->req_nb_sectors = 1;
+ ide_sector_read(s);
+ break;
case WIN_WRITE_EXT:
- lba48 = 1;
- case WIN_WRITE:
- case WIN_WRITE_ONCE:
- case CFA_WRITE_SECT_WO_ERASE:
- case WIN_WRITE_VERIFY:
- ide_cmd_lba48_transform(s, lba48);
- s->error = 0;
- s->status = SEEK_STAT | READY_STAT;
- s->req_nb_sectors = 1;
- ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
- s->media_changed = 1;
- break;
+ lba48 = 1;
+ case WIN_WRITE:
+ case WIN_WRITE_ONCE:
+ case CFA_WRITE_SECT_WO_ERASE:
+ case WIN_WRITE_VERIFY:
+ ide_cmd_lba48_transform(s, lba48);
+ s->error = 0;
+ s->status = SEEK_STAT | READY_STAT;
+ s->req_nb_sectors = 1;
+ ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
+ s->media_changed = 1;
+ break;
case WIN_MULTREAD_EXT:
- lba48 = 1;
- case WIN_MULTREAD:
- if (!s->mult_sectors)
- goto abort_cmd;
- ide_cmd_lba48_transform(s, lba48);
- s->req_nb_sectors = s->mult_sectors;
- ide_sector_read(s);
- break;
- case WIN_MULTWRITE_EXT:
- lba48 = 1;
- case WIN_MULTWRITE:
- case CFA_WRITE_MULTI_WO_ERASE:
- if (!s->mult_sectors)
- goto abort_cmd;
- ide_cmd_lba48_transform(s, lba48);
- s->error = 0;
- s->status = SEEK_STAT | READY_STAT;
- s->req_nb_sectors = s->mult_sectors;
- n = s->nsector;
- if (n > s->req_nb_sectors)
- n = s->req_nb_sectors;
- ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
- s->media_changed = 1;
- break;
+ lba48 = 1;
+ case WIN_MULTREAD:
+ if (!s->mult_sectors)
+ goto abort_cmd;
+ ide_cmd_lba48_transform(s, lba48);
+ s->req_nb_sectors = s->mult_sectors;
+ ide_sector_read(s);
+ break;
+ case WIN_MULTWRITE_EXT:
+ lba48 = 1;
+ case WIN_MULTWRITE:
+ case CFA_WRITE_MULTI_WO_ERASE:
+ if (!s->mult_sectors)
+ goto abort_cmd;
+ ide_cmd_lba48_transform(s, lba48);
+ s->error = 0;
+ s->status = SEEK_STAT | READY_STAT;
+ s->req_nb_sectors = s->mult_sectors;
+ n = s->nsector;
+ if (n > s->req_nb_sectors)
+ n = s->req_nb_sectors;
+ ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
+ s->media_changed = 1;
+ break;
case WIN_READDMA_EXT:
- lba48 = 1;
- case WIN_READDMA:
- case WIN_READDMA_ONCE:
- if (!s->bs)
- goto abort_cmd;
- ide_cmd_lba48_transform(s, lba48);
- ide_sector_read_dma(s);
- break;
+ lba48 = 1;
+ case WIN_READDMA:
+ case WIN_READDMA_ONCE:
+ if (!s->bs)
+ goto abort_cmd;
+ ide_cmd_lba48_transform(s, lba48);
+ ide_sector_read_dma(s);
+ break;
case WIN_WRITEDMA_EXT:
- lba48 = 1;
- case WIN_WRITEDMA:
- case WIN_WRITEDMA_ONCE:
- if (!s->bs)
- goto abort_cmd;
- ide_cmd_lba48_transform(s, lba48);
- ide_sector_write_dma(s);
- s->media_changed = 1;
- break;
- case WIN_READ_NATIVE_MAX_EXT:
- lba48 = 1;
- case WIN_READ_NATIVE_MAX:
- ide_cmd_lba48_transform(s, lba48);
- ide_set_sector(s, s->nb_sectors - 1);
- s->status = READY_STAT | SEEK_STAT;
- ide_set_irq(s->bus);
- break;
- case WIN_CHECKPOWERMODE1:
- case WIN_CHECKPOWERMODE2:
- s->nsector = 0xff; /* device active or idle */
+ lba48 = 1;
+ case WIN_WRITEDMA:
+ case WIN_WRITEDMA_ONCE:
+ if (!s->bs)
+ goto abort_cmd;
+ ide_cmd_lba48_transform(s, lba48);
+ ide_sector_write_dma(s);
+ s->media_changed = 1;
+ break;
+ case WIN_READ_NATIVE_MAX_EXT:
+ lba48 = 1;
+ case WIN_READ_NATIVE_MAX:
+ ide_cmd_lba48_transform(s, lba48);
+ ide_set_sector(s, s->nb_sectors - 1);
+ s->status = READY_STAT | SEEK_STAT;
+ ide_set_irq(s->bus);
+ break;
+ case WIN_CHECKPOWERMODE1:
+ case WIN_CHECKPOWERMODE2:
+ s->nsector = 0xff; /* device active or idle */
+ s->status = READY_STAT | SEEK_STAT;
+ ide_set_irq(s->bus);
+ break;
+ case WIN_SETFEATURES:
+ if (!s->bs)
+ goto abort_cmd;
+ /* XXX: valid for CDROM ? */
+ switch(s->feature) {
+ case 0xcc: /* reverting to power-on defaults enable */
+ case 0x66: /* reverting to power-on defaults disable */
+ case 0x02: /* write cache enable */
+ case 0x82: /* write cache disable */
+ case 0xaa: /* read look-ahead enable */
+ case 0x55: /* read look-ahead disable */
+ case 0x05: /* set advanced power management mode */
+ case 0x85: /* disable advanced power management mode */
+ case 0x69: /* NOP */
+ case 0x67: /* NOP */
+ case 0x96: /* NOP */
+ case 0x9a: /* NOP */
+ case 0x42: /* enable Automatic Acoustic Mode */
+ case 0xc2: /* disable Automatic Acoustic Mode */
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s->bus);
break;
- case WIN_SETFEATURES:
- if (!s->bs)
- goto abort_cmd;
- /* XXX: valid for CDROM ? */
- switch(s->feature) {
- case 0xcc: /* reverting to power-on defaults enable */
- case 0x66: /* reverting to power-on defaults disable */
- case 0x02: /* write cache enable */
- case 0x82: /* write cache disable */
- case 0xaa: /* read look-ahead enable */
- case 0x55: /* read look-ahead disable */
- case 0x05: /* set advanced power management mode */
- case 0x85: /* disable advanced power management mode */
- case 0x69: /* NOP */
- case 0x67: /* NOP */
- case 0x96: /* NOP */
- case 0x9a: /* NOP */
- case 0x42: /* enable Automatic Acoustic Mode */
- case 0xc2: /* disable Automatic Acoustic Mode */
- s->status = READY_STAT | SEEK_STAT;
- ide_set_irq(s->bus);
- break;
- case 0x03: { /* set transfer mode */
+ case 0x03: { /* set transfer mode */
uint8_t val = s->nsector & 0x07;
- uint16_t *identify_data = (uint16_t *)s->identify_data;
+ uint16_t *identify_data = (uint16_t *)s->identify_data;
switch (s->nsector >> 3) {
- case 0x00: /* pio default */
- case 0x01: /* pio mode */
+ case 0x00: /* pio default */
+ case 0x01: /* pio mode */
put_le16(identify_data + 62,0x07);
put_le16(identify_data + 63,0x07);
put_le16(identify_data + 88,0x3f);
break;
- case 0x02: /* sigle word dma mode*/
+ case 0x02: /* sigle word dma mode*/
put_le16(identify_data + 62,0x07 | (1 << (val + 8)));
put_le16(identify_data + 63,0x07);
put_le16(identify_data + 88,0x3f);
break;
- case 0x04: /* mdma mode */
+ case 0x04: /* mdma mode */
put_le16(identify_data + 62,0x07);
put_le16(identify_data + 63,0x07 | (1 << (val + 8)));
put_le16(identify_data + 88,0x3f);
break;
- case 0x08: /* udma mode */
+ case 0x08: /* udma mode */
put_le16(identify_data + 62,0x07);
put_le16(identify_data + 63,0x07);
put_le16(identify_data + 88,0x3f | (1 << (val + 8)));
break;
- default:
+ default:
goto abort_cmd;
}
- s->status = READY_STAT | SEEK_STAT;
- ide_set_irq(s->bus);
- break;
- }
- default:
- goto abort_cmd;
- }
- break;
- case WIN_FLUSH_CACHE:
- case WIN_FLUSH_CACHE_EXT:
- ide_flush_cache(s);
- break;
- case WIN_STANDBY:
- case WIN_STANDBY2:
- case WIN_STANDBYNOW1:
- case WIN_STANDBYNOW2:
- case WIN_IDLEIMMEDIATE:
- case CFA_IDLEIMMEDIATE:
- case WIN_SETIDLE1:
- case WIN_SETIDLE2:
- case WIN_SLEEPNOW1:
- case WIN_SLEEPNOW2:
- s->status = READY_STAT;
- ide_set_irq(s->bus);
- break;
- case WIN_SEEK:
- if(s->drive_kind == IDE_CD)
- goto abort_cmd;
- /* XXX: Check that seek is within bounds */
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s->bus);
break;
- /* ATAPI commands */
- case WIN_PIDENTIFY:
- if (s->drive_kind == IDE_CD) {
- ide_atapi_identify(s);
- s->status = READY_STAT | SEEK_STAT;
- ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
- } else {
- ide_abort_command(s);
- }
- ide_set_irq(s->bus);
- break;
- case WIN_DIAGNOSE:
- ide_set_signature(s);
- if (s->drive_kind == IDE_CD)
- s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet
- * devices to return a clear status register
- * with READY_STAT *not* set. */
- else
- s->status = READY_STAT | SEEK_STAT;
- s->error = 0x01; /* Device 0 passed, Device 1 passed or not
- * present.
- */
- ide_set_irq(s->bus);
- break;
- case WIN_SRST:
- if (s->drive_kind != IDE_CD)
- goto abort_cmd;
- ide_set_signature(s);
- s->status = 0x00; /* NOTE: READY is _not_ set */
- s->error = 0x01;
- break;
- case WIN_PACKETCMD:
- if (s->drive_kind != IDE_CD)
- goto abort_cmd;
- /* overlapping commands not supported */
- if (s->feature & 0x02)
- goto abort_cmd;
+ }
+ default:
+ goto abort_cmd;
+ }
+ break;
+ case WIN_FLUSH_CACHE:
+ case WIN_FLUSH_CACHE_EXT:
+ ide_flush_cache(s);
+ break;
+ case WIN_STANDBY:
+ case WIN_STANDBY2:
+ case WIN_STANDBYNOW1:
+ case WIN_STANDBYNOW2:
+ case WIN_IDLEIMMEDIATE:
+ case CFA_IDLEIMMEDIATE:
+ case WIN_SETIDLE1:
+ case WIN_SETIDLE2:
+ case WIN_SLEEPNOW1:
+ case WIN_SLEEPNOW2:
+ s->status = READY_STAT;
+ ide_set_irq(s->bus);
+ break;
+ case WIN_SEEK:
+ if(s->drive_kind == IDE_CD)
+ goto abort_cmd;
+ /* XXX: Check that seek is within bounds */
+ s->status = READY_STAT | SEEK_STAT;
+ ide_set_irq(s->bus);
+ break;
+ /* ATAPI commands */
+ case WIN_PIDENTIFY:
+ if (s->drive_kind == IDE_CD) {
+ ide_atapi_identify(s);
s->status = READY_STAT | SEEK_STAT;
- s->atapi_dma = s->feature & 1;
- s->nsector = 1;
- ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
- ide_atapi_cmd);
- break;
- /* CF-ATA commands */
- case CFA_REQ_EXT_ERROR_CODE:
- if (s->drive_kind != IDE_CFATA)
- goto abort_cmd;
- s->error = 0x09; /* miscellaneous error */
+ ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
+ } else {
+ ide_abort_command(s);
+ }
+ ide_set_irq(s->bus);
+ break;
+ case WIN_DIAGNOSE:
+ ide_set_signature(s);
+ if (s->drive_kind == IDE_CD)
+ s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet
+ * devices to return a clear status register
+ * with READY_STAT *not* set. */
+ else
s->status = READY_STAT | SEEK_STAT;
- ide_set_irq(s->bus);
+ s->error = 0x01; /* Device 0 passed, Device 1 passed or not
+ * present.
+ */
+ ide_set_irq(s->bus);
+ break;
+ case WIN_SRST:
+ if (s->drive_kind != IDE_CD)
+ goto abort_cmd;
+ ide_set_signature(s);
+ s->status = 0x00; /* NOTE: READY is _not_ set */
+ s->error = 0x01;
+ break;
+ case WIN_PACKETCMD:
+ if (s->drive_kind != IDE_CD)
+ goto abort_cmd;
+ /* overlapping commands not supported */
+ if (s->feature & 0x02)
+ goto abort_cmd;
+ s->status = READY_STAT | SEEK_STAT;
+ s->atapi_dma = s->feature & 1;
+ s->nsector = 1;
+ ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
+ ide_atapi_cmd);
+ break;
+ /* CF-ATA commands */
+ case CFA_REQ_EXT_ERROR_CODE:
+ if (s->drive_kind != IDE_CFATA)
+ goto abort_cmd;
+ s->error = 0x09; /* miscellaneous error */
+ s->status = READY_STAT | SEEK_STAT;
+ ide_set_irq(s->bus);
+ break;
+ case CFA_ERASE_SECTORS:
+ case CFA_WEAR_LEVEL:
+ if (s->drive_kind != IDE_CFATA)
+ goto abort_cmd;
+ if (val == CFA_WEAR_LEVEL)
+ s->nsector = 0;
+ if (val == CFA_ERASE_SECTORS)
+ s->media_changed = 1;
+ s->error = 0x00;
+ s->status = READY_STAT | SEEK_STAT;
+ ide_set_irq(s->bus);
+ break;
+ case CFA_TRANSLATE_SECTOR:
+ if (s->drive_kind != IDE_CFATA)
+ goto abort_cmd;
+ s->error = 0x00;
+ s->status = READY_STAT | SEEK_STAT;
+ memset(s->io_buffer, 0, 0x200);
+ s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
+ s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
+ s->io_buffer[0x02] = s->select; /* Head */
+ s->io_buffer[0x03] = s->sector; /* Sector */
+ s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
+ s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
+ s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
+ s->io_buffer[0x13] = 0x00; /* Erase flag */
+ s->io_buffer[0x18] = 0x00; /* Hot count */
+ s->io_buffer[0x19] = 0x00; /* Hot count */
+ s->io_buffer[0x1a] = 0x01; /* Hot count */
+ ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
+ ide_set_irq(s->bus);
+ break;
+ case CFA_ACCESS_METADATA_STORAGE:
+ if (s->drive_kind != IDE_CFATA)
+ goto abort_cmd;
+ switch (s->feature) {
+ case 0x02: /* Inquiry Metadata Storage */
+ ide_cfata_metadata_inquiry(s);
break;
- case CFA_ERASE_SECTORS:
- case CFA_WEAR_LEVEL:
- if (s->drive_kind != IDE_CFATA)
- goto abort_cmd;
- if (val == CFA_WEAR_LEVEL)
- s->nsector = 0;
- if (val == CFA_ERASE_SECTORS)
- s->media_changed = 1;
- s->error = 0x00;
- s->status = READY_STAT | SEEK_STAT;
- ide_set_irq(s->bus);
+ case 0x03: /* Read Metadata Storage */
+ ide_cfata_metadata_read(s);
break;
- case CFA_TRANSLATE_SECTOR:
- if (s->drive_kind != IDE_CFATA)
- goto abort_cmd;
- s->error = 0x00;
- s->status = READY_STAT | SEEK_STAT;
- memset(s->io_buffer, 0, 0x200);
- s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
- s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
- s->io_buffer[0x02] = s->select; /* Head */
- s->io_buffer[0x03] = s->sector; /* Sector */
- s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
- s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
- s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
- s->io_buffer[0x13] = 0x00; /* Erase flag */
- s->io_buffer[0x18] = 0x00; /* Hot count */
- s->io_buffer[0x19] = 0x00; /* Hot count */
- s->io_buffer[0x1a] = 0x01; /* Hot count */
- ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
- ide_set_irq(s->bus);
+ case 0x04: /* Write Metadata Storage */
+ ide_cfata_metadata_write(s);
break;
- case CFA_ACCESS_METADATA_STORAGE:
- if (s->drive_kind != IDE_CFATA)
- goto abort_cmd;
- switch (s->feature) {
- case 0x02: /* Inquiry Metadata Storage */
- ide_cfata_metadata_inquiry(s);
- break;
- case 0x03: /* Read Metadata Storage */
- ide_cfata_metadata_read(s);
- break;
- case 0x04: /* Write Metadata Storage */
- ide_cfata_metadata_write(s);
- break;
- default:
- goto abort_cmd;
- }
- ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
- s->status = 0x00; /* NOTE: READY is _not_ set */
- ide_set_irq(s->bus);
- break;
- case IBM_SENSE_CONDITION:
- if (s->drive_kind != IDE_CFATA)
- goto abort_cmd;
- switch (s->feature) {
- case 0x01: /* sense temperature in device */
- s->nsector = 0x50; /* +20 C */
- break;
- default:
- goto abort_cmd;
- }
- s->status = READY_STAT | SEEK_STAT;
- ide_set_irq(s->bus);
+ default:
+ goto abort_cmd;
+ }
+ ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
+ s->status = 0x00; /* NOTE: READY is _not_ set */
+ ide_set_irq(s->bus);
+ break;
+ case IBM_SENSE_CONDITION:
+ if (s->drive_kind != IDE_CFATA)
+ goto abort_cmd;
+ switch (s->feature) {
+ case 0x01: /* sense temperature in device */
+ s->nsector = 0x50; /* +20 C */
break;
+ default:
+ goto abort_cmd;
+ }
+ s->status = READY_STAT | SEEK_STAT;
+ ide_set_irq(s->bus);
+ break;
case WIN_SMART:
- if (s->drive_kind == IDE_CD)
+ if (s->drive_kind == IDE_CD)
goto abort_cmd;
- if (s->hcyl != 0xc2 || s->lcyl != 0x4f)
+ if (s->hcyl != 0xc2 || s->lcyl != 0x4f)
goto abort_cmd;
- if (!s->smart_enabled && s->feature != SMART_ENABLE)
+ if (!s->smart_enabled && s->feature != SMART_ENABLE)
goto abort_cmd;
- switch (s->feature) {
- case SMART_DISABLE:
+ switch (s->feature) {
+ case SMART_DISABLE:
s->smart_enabled = 0;
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s->bus);
break;
- case SMART_ENABLE:
+ case SMART_ENABLE:
s->smart_enabled = 1;
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s->bus);
break;
- case SMART_ATTR_AUTOSAVE:
+ case SMART_ATTR_AUTOSAVE:
switch (s->sector) {
case 0x00:
- s->smart_autosave = 0;
- break;
+ s->smart_autosave = 0;
+ break;
case 0xf1:
- s->smart_autosave = 1;
- break;
+ s->smart_autosave = 1;
+ break;
default:
- goto abort_cmd;
+ goto abort_cmd;
}
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s->bus);
break;
- case SMART_STATUS:
+ case SMART_STATUS:
if (!s->smart_errors) {
- s->hcyl = 0xc2;
- s->lcyl = 0x4f;
+ s->hcyl = 0xc2;
+ s->lcyl = 0x4f;
} else {
- s->hcyl = 0x2c;
- s->lcyl = 0xf4;
+ s->hcyl = 0x2c;
+ s->lcyl = 0xf4;
}
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s->bus);
break;
- case SMART_READ_THRESH:
+ case SMART_READ_THRESH:
memset(s->io_buffer, 0, 0x200);
s->io_buffer[0] = 0x01; /* smart struct version */
for (n=0; n<30; n++) {
- if (smart_attributes[n][0] == 0)
+ if (smart_attributes[n][0] == 0)
break;
- s->io_buffer[2+0+(n*12)] = smart_attributes[n][0];
- s->io_buffer[2+1+(n*12)] = smart_attributes[n][4];
+ s->io_buffer[2+0+(n*12)] = smart_attributes[n][0];
+ s->io_buffer[2+1+(n*12)] = smart_attributes[n][4];
}
for (n=0; n<511; n++) /* checksum */
- s->io_buffer[511] += s->io_buffer[n];
+ s->io_buffer[511] += s->io_buffer[n];
s->io_buffer[511] = 0x100 - s->io_buffer[511];
s->status = READY_STAT | SEEK_STAT;
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
ide_set_irq(s->bus);
break;
- case SMART_READ_DATA:
+ case SMART_READ_DATA:
memset(s->io_buffer, 0, 0x200);
s->io_buffer[0] = 0x01; /* smart struct version */
for (n=0; n<30; n++) {
- if (smart_attributes[n][0] == 0)
+ if (smart_attributes[n][0] == 0)
break;
- s->io_buffer[2+0+(n*12)] = smart_attributes[n][0];
- s->io_buffer[2+1+(n*12)] = smart_attributes[n][1];
- s->io_buffer[2+3+(n*12)] = smart_attributes[n][2];
- s->io_buffer[2+4+(n*12)] = smart_attributes[n][3];
+ s->io_buffer[2+0+(n*12)] = smart_attributes[n][0];
+ s->io_buffer[2+1+(n*12)] = smart_attributes[n][1];
+ s->io_buffer[2+3+(n*12)] = smart_attributes[n][2];
+ s->io_buffer[2+4+(n*12)] = smart_attributes[n][3];
}
s->io_buffer[362] = 0x02 | (s->smart_autosave?0x80:0x00);
if (s->smart_selftest_count == 0) {
- s->io_buffer[363] = 0;
+ s->io_buffer[363] = 0;
} else {
- s->io_buffer[363] =
+ s->io_buffer[363] =
s->smart_selftest_data[3 +
- (s->smart_selftest_count - 1) *
- 24];
+ (s->smart_selftest_count - 1) *
+ 24];
}
s->io_buffer[364] = 0x20;
s->io_buffer[365] = 0x01;
@@ -2293,76 +2293,76 @@ void ide_exec_cmd(IDEBus *bus, uint32_t val)
s->io_buffer[374] = 0x01; /* minutes for poll conveyance */
for (n=0; n<511; n++)
- s->io_buffer[511] += s->io_buffer[n];
+ s->io_buffer[511] += s->io_buffer[n];
s->io_buffer[511] = 0x100 - s->io_buffer[511];
s->status = READY_STAT | SEEK_STAT;
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
ide_set_irq(s->bus);
break;
- case SMART_READ_LOG:
+ case SMART_READ_LOG:
switch (s->sector) {
case 0x01: /* summary smart error log */
- memset(s->io_buffer, 0, 0x200);
- s->io_buffer[0] = 0x01;
- s->io_buffer[1] = 0x00; /* no error entries */
- s->io_buffer[452] = s->smart_errors & 0xff;
- s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8;
+ memset(s->io_buffer, 0, 0x200);
+ s->io_buffer[0] = 0x01;
+ s->io_buffer[1] = 0x00; /* no error entries */
+ s->io_buffer[452] = s->smart_errors & 0xff;
+ s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8;
- for (n=0; n<511; n++)
+ for (n=0; n<511; n++)
s->io_buffer[511] += s->io_buffer[n];
- s->io_buffer[511] = 0x100 - s->io_buffer[511];
- break;
+ s->io_buffer[511] = 0x100 - s->io_buffer[511];
+ break;
case 0x06: /* smart self test log */
- memset(s->io_buffer, 0, 0x200);
- s->io_buffer[0] = 0x01;
- if (s->smart_selftest_count == 0) {
+ memset(s->io_buffer, 0, 0x200);
+ s->io_buffer[0] = 0x01;
+ if (s->smart_selftest_count == 0) {
s->io_buffer[508] = 0;
- } else {
+ } else {
s->io_buffer[508] = s->smart_selftest_count;
for (n=2; n<506; n++)
- s->io_buffer[n] = s->smart_selftest_data[n];
- }
- for (n=0; n<511; n++)
+ s->io_buffer[n] = s->smart_selftest_data[n];
+ }
+ for (n=0; n<511; n++)
s->io_buffer[511] += s->io_buffer[n];
- s->io_buffer[511] = 0x100 - s->io_buffer[511];
- break;
+ s->io_buffer[511] = 0x100 - s->io_buffer[511];
+ break;
default:
- goto abort_cmd;
+ goto abort_cmd;
}
s->status = READY_STAT | SEEK_STAT;
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
ide_set_irq(s->bus);
break;
- case SMART_EXECUTE_OFFLINE:
+ case SMART_EXECUTE_OFFLINE:
switch (s->sector) {
case 0: /* off-line routine */
case 1: /* short self test */
case 2: /* extended self test */
- s->smart_selftest_count++;
- if(s->smart_selftest_count > 21)
+ s->smart_selftest_count++;
+ if(s->smart_selftest_count > 21)
s->smart_selftest_count = 0;
- n = 2 + (s->smart_selftest_count - 1) * 24;
- s->smart_selftest_data[n] = s->sector;
- s->smart_selftest_data[n+1] = 0x00; /* OK and finished */
- s->smart_selftest_data[n+2] = 0x34; /* hour count lsb */
- s->smart_selftest_data[n+3] = 0x12; /* hour count msb */
- s->status = READY_STAT | SEEK_STAT;
- ide_set_irq(s->bus);
- break;
+ n = 2 + (s->smart_selftest_count - 1) * 24;
+ s->smart_selftest_data[n] = s->sector;
+ s->smart_selftest_data[n+1] = 0x00; /* OK and finished */
+ s->smart_selftest_data[n+2] = 0x34; /* hour count lsb */
+ s->smart_selftest_data[n+3] = 0x12; /* hour count msb */
+ s->status = READY_STAT | SEEK_STAT;
+ ide_set_irq(s->bus);
+ break;
default:
- goto abort_cmd;
+ goto abort_cmd;
}
break;
- default:
+ default:
goto abort_cmd;
- }
- break;
- default:
- abort_cmd:
- ide_abort_command(s);
- ide_set_irq(s->bus);
- break;
- }
+ }
+ break;
+ default:
+ abort_cmd:
+ ide_abort_command(s);
+ ide_set_irq(s->bus);
+ break;
+ }
}
uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
--
1.6.0.2
^ permalink raw reply related [flat|nested] 18+ messages in thread* [Qemu-devel] [PATCH 03/10] ide: add support for ide extenders
2010-11-17 1:05 [Qemu-devel] [PATCH 00/10] AHCI emulation support Alexander Graf
2010-11-17 1:05 ` [Qemu-devel] [PATCH 01/10] ide: split ide command interpretation off Alexander Graf
2010-11-17 1:05 ` [Qemu-devel] [PATCH 02/10] ide: fix whitespace gap in ide_exec_cmd Alexander Graf
@ 2010-11-17 1:05 ` Alexander Graf
2010-11-17 8:57 ` Gerd Hoffmann
2010-11-17 1:05 ` [Qemu-devel] [PATCH 04/10] ide: enable preallocated sg lists Alexander Graf
` (6 subsequent siblings)
9 siblings, 1 reply; 18+ messages in thread
From: Alexander Graf @ 2010-11-17 1:05 UTC (permalink / raw)
To: QEMU-devel Developers; +Cc: tj, Joerg Roedel, Sebastian Herbszt, Roland Elek
From: Roland Elek <elek.roland@gmail.com>
An "extender" (from the "extends" keyword denoting a subclass in
various object-oriented languages) is a device that builds upon an
IDE bus, but needs to change various aspects of its inner workings
to customize it to its needs. An example of an extender is an AHCI
HBA. We add support for extenders by defining a struct that contains
callback function pointers that can be set by the device building
upon the bus. The IDE core was modified so that ide_transfer_start,
ide_set_irq and ide_dma_start call the function pointed to by the
respective field in the extender struct, instead of doing their
original jobs. The original functions are available as
pata_transfer_start, pata_set_irq and pata_dma_start. The extender
callbacks are initialized to these in ide_init2, making them the
defaults, and eliminating the need to modify ATA controller code.
Signed-off-by: Roland Elek <elek.roland@gmail.com>
---
hw/ide/core.c | 34 +++++++++++++++++++++++++++++++++-
hw/ide/internal.h | 26 +++++++++++++++++++-------
2 files changed, 52 insertions(+), 8 deletions(-)
diff --git a/hw/ide/core.c b/hw/ide/core.c
index 1849069..276b853 100644
--- a/hw/ide/core.c
+++ b/hw/ide/core.c
@@ -67,6 +67,8 @@ static void ide_atapi_cmd_read_dma_cb(void *opaque, int ret);
static int ide_handle_rw_error(IDEState *s, int error, int op);
static void ide_flush_cache(IDEState *s);
+static void pata_dma_start(IDEState *s, BlockDriverCompletionFunc *dma_cb);
+
static void padstr(char *str, const char *src, int len)
{
int i, v;
@@ -325,6 +327,12 @@ static inline void ide_dma_submit_check(IDEState *s,
static void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
EndTransferFunc *end_transfer_func)
{
+ s->bus->extender.transfer_start_fn(s,buf,size,end_transfer_func);
+}
+
+static void pata_transfer_start(IDEState *s, uint8_t *buf, int size,
+ EndTransferFunc *end_transfer_func)
+{
s->end_transfer_func = end_transfer_func;
s->data_ptr = buf;
s->data_end = buf + size;
@@ -2580,6 +2588,18 @@ static void ide_dummy_transfer_stop(IDEState *s)
s->io_buffer[3] = 0xff;
}
+static void pata_set_irq(IDEBus *bus)
+{
+ BMDMAState *bm = bus->bmdma;
+
+ if (!(bus->cmd & IDE_CMD_DISABLE_IRQ)) {
+ if (bm) {
+ bm->status |= BM_STATUS_INT;
+ }
+ qemu_irq_raise(bus->irq);
+ }
+}
+
static void ide_reset(IDEState *s)
{
#ifdef DEBUG_IDE
@@ -2725,6 +2745,9 @@ void ide_init2(IDEBus *bus, qemu_irq irq)
ide_reset(&bus->ifs[i]);
}
bus->irq = irq;
+ bus->extender.transfer_start_fn = pata_transfer_start;
+ bus->extender.irq_set_fn = pata_set_irq;
+ bus->extender.dma_start_fn = pata_dma_start;
}
/* TODO convert users to qdev and remove */
@@ -2748,6 +2771,9 @@ void ide_init2_with_non_qdev_drives(IDEBus *bus, DriveInfo *hd0,
}
}
bus->irq = irq;
+ bus->extender.transfer_start_fn = pata_transfer_start;
+ bus->extender.irq_set_fn = pata_set_irq;
+ bus->extender.dma_start_fn = pata_dma_start;
}
void ide_init_ioport(IDEBus *bus, int iobase, int iobase2)
@@ -2919,9 +2945,10 @@ const VMStateDescription vmstate_ide_bus = {
/***********************************************************/
/* PCI IDE definitions */
-static void ide_dma_start(IDEState *s, BlockDriverCompletionFunc *dma_cb)
+static void pata_dma_start(IDEState *s, BlockDriverCompletionFunc *dma_cb)
{
BMDMAState *bm = s->bus->bmdma;
+
if(!bm)
return;
bm->unit = s->unit;
@@ -2936,6 +2963,11 @@ static void ide_dma_start(IDEState *s, BlockDriverCompletionFunc *dma_cb)
}
}
+static void ide_dma_start(IDEState *s, BlockDriverCompletionFunc *dma_cb)
+{
+ s->bus->extender.dma_start_fn(s,dma_cb);
+}
+
static void ide_dma_restart(IDEState *s, int is_read)
{
BMDMAState *bm = s->bus->bmdma;
diff --git a/hw/ide/internal.h b/hw/ide/internal.h
index e7e1f80..19e5efb 100644
--- a/hw/ide/internal.h
+++ b/hw/ide/internal.h
@@ -20,6 +20,7 @@ typedef struct IDEDevice IDEDevice;
typedef struct IDEDeviceInfo IDEDeviceInfo;
typedef struct IDEState IDEState;
typedef struct BMDMAState BMDMAState;
+typedef struct IDEExtender IDEExtender;
/* Bits of HD_STATUS */
#define ERR_STAT 0x01
@@ -366,6 +367,14 @@ typedef enum { IDE_HD, IDE_CD, IDE_CFATA } IDEDriveKind;
typedef void EndTransferFunc(IDEState *);
+
+typedef void TransferStartFunc(IDEState *,
+ uint8_t *,
+ int,
+ EndTransferFunc *);
+typedef void IRQSetFunc(IDEBus *);
+typedef void DMAStartFunc(IDEState *, BlockDriverCompletionFunc *);
+
/* NOTE: IDEState represents in fact one drive */
struct IDEState {
IDEBus *bus;
@@ -442,12 +451,21 @@ struct IDEState {
uint8_t *smart_selftest_data;
};
+/* This struct represents a device that uses an IDE bus, but requires
+ * modifications to how it works. An example is AHCI. */
+struct IDEExtender {
+ TransferStartFunc *transfer_start_fn;
+ IRQSetFunc *irq_set_fn;
+ DMAStartFunc *dma_start_fn;
+};
+
struct IDEBus {
BusState qbus;
IDEDevice *master;
IDEDevice *slave;
BMDMAState *bmdma;
IDEState ifs[2];
+ IDEExtender extender;
uint8_t unit;
uint8_t cmd;
qemu_irq irq;
@@ -512,13 +530,7 @@ static inline IDEState *bmdma_active_if(BMDMAState *bmdma)
static inline void ide_set_irq(IDEBus *bus)
{
- BMDMAState *bm = bus->bmdma;
- if (!(bus->cmd & IDE_CMD_DISABLE_IRQ)) {
- if (bm) {
- bm->status |= BM_STATUS_INT;
- }
- qemu_irq_raise(bus->irq);
- }
+ bus->extender.irq_set_fn(bus);
}
/* hw/ide/core.c */
--
1.6.0.2
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [Qemu-devel] [PATCH 03/10] ide: add support for ide extenders
2010-11-17 1:05 ` [Qemu-devel] [PATCH 03/10] ide: add support for ide extenders Alexander Graf
@ 2010-11-17 8:57 ` Gerd Hoffmann
0 siblings, 0 replies; 18+ messages in thread
From: Gerd Hoffmann @ 2010-11-17 8:57 UTC (permalink / raw)
To: Alexander Graf
Cc: tj, Joerg Roedel, Roland Elek, QEMU-devel Developers,
Sebastian Herbszt
Hi,
> +/* This struct represents a device that uses an IDE bus, but requires
> + * modifications to how it works. An example is AHCI. */
> +struct IDEExtender {
> + TransferStartFunc *transfer_start_fn;
> + IRQSetFunc *irq_set_fn;
> + DMAStartFunc *dma_start_fn;
> +};
Hmm, I'd call that IDEBusOps or simliar.
> struct IDEBus {
> BusState qbus;
> IDEDevice *master;
> IDEDevice *slave;
> BMDMAState *bmdma;
> IDEState ifs[2];
> + IDEExtender extender;
IDEBusOps *ops;
Note this is a pointer now, so you can have static IDEBusOps structs and
just set the ops pointer instead of filling in three function pointers.
cheers,
Gerd
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH 04/10] ide: enable preallocated sg lists
2010-11-17 1:05 [Qemu-devel] [PATCH 00/10] AHCI emulation support Alexander Graf
` (2 preceding siblings ...)
2010-11-17 1:05 ` [Qemu-devel] [PATCH 03/10] ide: add support for ide extenders Alexander Graf
@ 2010-11-17 1:05 ` Alexander Graf
2010-11-17 8:59 ` Gerd Hoffmann
2010-11-17 9:21 ` Stefan Hajnoczi
2010-11-17 1:05 ` [Qemu-devel] [PATCH 05/10] ide: add ncq identify data for ahci sata drives Alexander Graf
` (5 subsequent siblings)
9 siblings, 2 replies; 18+ messages in thread
From: Alexander Graf @ 2010-11-17 1:05 UTC (permalink / raw)
To: QEMU-devel Developers; +Cc: tj, Joerg Roedel, Sebastian Herbszt, Roland Elek
The AHCI core does all the SG handling for us, so we need to allow it
to keep its own layouts.
This patch adds hooks into the IDE code to allow for preallocated SG lists.
Signed-off-by: Roland Elek <elek.roland@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
hw/ide/core.c | 38 +++++++++++++++++++++++++++++++-------
hw/ide/internal.h | 1 +
2 files changed, 32 insertions(+), 7 deletions(-)
diff --git a/hw/ide/core.c b/hw/ide/core.c
index 276b853..4c15ea2 100644
--- a/hw/ide/core.c
+++ b/hw/ide/core.c
@@ -444,8 +444,16 @@ static int dma_buf_prepare(BMDMAState *bm, int is_write)
uint32_t addr;
uint32_t size;
} prd;
- int l, len;
+ int l, len, i;
+ if (s->sg_third_party) {
+ /* We already have an sglist. */
+ s->io_buffer_size = 0;
+ for (i=0; i < s->sg.nsg; i++) {
+ s->io_buffer_size += s->sg.sg[i].len;
+ }
+ return s->io_buffer_size != 0;
+ }
qemu_sglist_init(&s->sg, s->nsector / (IDE_PAGE_SIZE / 512) + 1);
s->io_buffer_size = 0;
for(;;) {
@@ -535,12 +543,25 @@ static int dma_buf_rw(BMDMAState *bm, int is_write)
if (bm->cur_prd_len == 0) {
/* end of table (with a fail safe of one page) */
if (bm->cur_prd_last ||
- (bm->cur_addr - bm->addr) >= IDE_PAGE_SIZE)
- return 0;
- cpu_physical_memory_read(bm->cur_addr, (uint8_t *)&prd, 8);
- bm->cur_addr += 8;
- prd.addr = le32_to_cpu(prd.addr);
- prd.size = le32_to_cpu(prd.size);
+ (bm->cur_addr - bm->addr) >= IDE_PAGE_SIZE) {
+ s->sg.sg -= s->sg.nsg; //XXX
+ return 0;
+ }
+ if (s->sg_third_party) {
+ /* We've already parsed the guest RAM PRDT.
+ * This is essential for AHCI, where the PRDT is in a different
+ * format than in IDE BMDMA.
+ */
+ memcpy((uint8_t *)&prd, s->sg.sg, sizeof(prd));
+ s->sg.sg++;
+ } else {
+ cpu_physical_memory_read(bm->cur_addr, (uint8_t *)&prd, 8);
+ bm->cur_addr += 8;
+ prd.addr = le32_to_cpu(prd.addr);
+ prd.size = le32_to_cpu(prd.size);
+ }
+
+
len = prd.size & 0xfffe;
if (len == 0)
len = 0x10000;
@@ -2715,6 +2736,9 @@ int ide_init_drive(IDEState *s, BlockDriverState *bs,
} else {
pstrcpy(s->version, sizeof(s->version), QEMU_VERSION);
}
+
+ s->sg_third_party = 0;
+
ide_reset(s);
bdrv_set_removable(bs, s->drive_kind == IDE_CD);
return 0;
diff --git a/hw/ide/internal.h b/hw/ide/internal.h
index 19e5efb..005283c 100644
--- a/hw/ide/internal.h
+++ b/hw/ide/internal.h
@@ -422,6 +422,7 @@ struct IDEState {
/* ATA DMA state */
int io_buffer_size;
QEMUSGList sg;
+ int sg_third_party;
/* PIO transfer handling */
int req_nb_sectors; /* number of sectors per interrupt */
EndTransferFunc *end_transfer_func;
--
1.6.0.2
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [Qemu-devel] [PATCH 04/10] ide: enable preallocated sg lists
2010-11-17 1:05 ` [Qemu-devel] [PATCH 04/10] ide: enable preallocated sg lists Alexander Graf
@ 2010-11-17 8:59 ` Gerd Hoffmann
2010-11-17 9:21 ` Stefan Hajnoczi
1 sibling, 0 replies; 18+ messages in thread
From: Gerd Hoffmann @ 2010-11-17 8:59 UTC (permalink / raw)
To: Alexander Graf
Cc: tj, Joerg Roedel, Roland Elek, QEMU-devel Developers,
Sebastian Herbszt
Hi,
> + if (s->sg_third_party) {
> + /* We've already parsed the guest RAM PRDT.
> + * This is essential for AHCI, where the PRDT is in a different
> + * format than in IDE BMDMA.
> + */
> + memcpy((uint8_t *)&prd, s->sg.sg, sizeof(prd));
> + s->sg.sg++;
> + } else {
> + cpu_physical_memory_read(bm->cur_addr, (uint8_t *)&prd, 8);
> + bm->cur_addr += 8;
> + prd.addr = le32_to_cpu(prd.addr);
> + prd.size = le32_to_cpu(prd.size);
> + }
Does it make sense to handle this via IDEBusOps too?
cheers,
Gerd
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [Qemu-devel] [PATCH 04/10] ide: enable preallocated sg lists
2010-11-17 1:05 ` [Qemu-devel] [PATCH 04/10] ide: enable preallocated sg lists Alexander Graf
2010-11-17 8:59 ` Gerd Hoffmann
@ 2010-11-17 9:21 ` Stefan Hajnoczi
1 sibling, 0 replies; 18+ messages in thread
From: Stefan Hajnoczi @ 2010-11-17 9:21 UTC (permalink / raw)
To: Alexander Graf
Cc: tj, Joerg Roedel, Roland Elek, QEMU-devel Developers,
Sebastian Herbszt
On Wed, Nov 17, 2010 at 1:05 AM, Alexander Graf <agraf@suse.de> wrote:
> @@ -535,12 +543,25 @@ static int dma_buf_rw(BMDMAState *bm, int is_write)
> if (bm->cur_prd_len == 0) {
> /* end of table (with a fail safe of one page) */
> if (bm->cur_prd_last ||
> - (bm->cur_addr - bm->addr) >= IDE_PAGE_SIZE)
> - return 0;
> - cpu_physical_memory_read(bm->cur_addr, (uint8_t *)&prd, 8);
> - bm->cur_addr += 8;
> - prd.addr = le32_to_cpu(prd.addr);
> - prd.size = le32_to_cpu(prd.size);
> + (bm->cur_addr - bm->addr) >= IDE_PAGE_SIZE) {
> + s->sg.sg -= s->sg.nsg; //XXX
I don't understand why s->sg.sg needs to be modified at all. Are we stashing
the pointer away accross dma_buf_rw() invocations?
> + return 0;
> + }
> + if (s->sg_third_party) {
> + /* We've already parsed the guest RAM PRDT.
> + * This is essential for AHCI, where the PRDT is in a different
> + * format than in IDE BMDMA.
> + */
> + memcpy((uint8_t *)&prd, s->sg.sg, sizeof(prd));
struct {
uint32_t addr;
uint32_t size;
} prd;
typedef struct {
target_phys_addr_t base;
target_phys_addr_t len;
} ScatterGatherEntry;
sizeof(target_phys_addr_t) != sizeof(uint32_t) for 64-bit targets
prd should use a proper struct instead of redefining it inline in dma_buf_rw()
and dma_buf_prepare(). That struct could either be a ScatterGatherEntry or
something else that we assign s->sg.sg fields to individually.
Stefan
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH 05/10] ide: add ncq identify data for ahci sata drives
2010-11-17 1:05 [Qemu-devel] [PATCH 00/10] AHCI emulation support Alexander Graf
` (3 preceding siblings ...)
2010-11-17 1:05 ` [Qemu-devel] [PATCH 04/10] ide: enable preallocated sg lists Alexander Graf
@ 2010-11-17 1:05 ` Alexander Graf
2010-11-17 1:05 ` [Qemu-devel] [PATCH 06/10] pci: add storage class for sata Alexander Graf
` (4 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Alexander Graf @ 2010-11-17 1:05 UTC (permalink / raw)
To: QEMU-devel Developers; +Cc: tj, Joerg Roedel, Sebastian Herbszt, Roland Elek
From: Roland Elek <elek.roland@gmail.com>
I modified ide_identify() to include the zero-based queue length
value in word 75, and set bit 8 in word 76 to signal NCQ support
in the identify data for AHCI SATA drives.
Signed-off-by: Roland Elek <elek.roland@gmail.com>
---
hw/ide/core.c | 7 +++++++
hw/ide/internal.h | 2 ++
2 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/hw/ide/core.c b/hw/ide/core.c
index 4c15ea2..8f858c0 100644
--- a/hw/ide/core.c
+++ b/hw/ide/core.c
@@ -147,6 +147,13 @@ static void ide_identify(IDEState *s)
put_le16(p + 66, 120);
put_le16(p + 67, 120);
put_le16(p + 68, 120);
+
+ if (s->ncq_queues) {
+ put_le16(p + 75, s->ncq_queues - 1);
+ /* NCQ supported */
+ put_le16(p + 76, (1 << 8));
+ }
+
put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
put_le16(p + 81, 0x16); /* conforms to ata5 */
/* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */
diff --git a/hw/ide/internal.h b/hw/ide/internal.h
index 005283c..7f31dd8 100644
--- a/hw/ide/internal.h
+++ b/hw/ide/internal.h
@@ -450,6 +450,8 @@ struct IDEState {
int smart_errors;
uint8_t smart_selftest_count;
uint8_t *smart_selftest_data;
+ /* AHCI */
+ int ncq_queues;
};
/* This struct represents a device that uses an IDE bus, but requires
--
1.6.0.2
^ permalink raw reply related [flat|nested] 18+ messages in thread* [Qemu-devel] [PATCH 06/10] pci: add storage class for sata
2010-11-17 1:05 [Qemu-devel] [PATCH 00/10] AHCI emulation support Alexander Graf
` (4 preceding siblings ...)
2010-11-17 1:05 ` [Qemu-devel] [PATCH 05/10] ide: add ncq identify data for ahci sata drives Alexander Graf
@ 2010-11-17 1:05 ` Alexander Graf
2010-11-17 1:05 ` [Qemu-devel] [PATCH 07/10] pci: add ich7 pci id Alexander Graf
` (3 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Alexander Graf @ 2010-11-17 1:05 UTC (permalink / raw)
To: QEMU-devel Developers; +Cc: tj, Joerg Roedel, Sebastian Herbszt, Roland Elek
This patch adds the storage sata class id.
Signed-off-by: Alexander Graf <agraf@suse.de>
---
hw/pci_ids.h | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/hw/pci_ids.h b/hw/pci_ids.h
index 82cba7e..ea3418c 100644
--- a/hw/pci_ids.h
+++ b/hw/pci_ids.h
@@ -15,6 +15,7 @@
#define PCI_CLASS_STORAGE_SCSI 0x0100
#define PCI_CLASS_STORAGE_IDE 0x0101
+#define PCI_CLASS_STORAGE_SATA 0x0106
#define PCI_CLASS_STORAGE_OTHER 0x0180
#define PCI_CLASS_NETWORK_ETHERNET 0x0200
--
1.6.0.2
^ permalink raw reply related [flat|nested] 18+ messages in thread* [Qemu-devel] [PATCH 07/10] pci: add ich7 pci id
2010-11-17 1:05 [Qemu-devel] [PATCH 00/10] AHCI emulation support Alexander Graf
` (5 preceding siblings ...)
2010-11-17 1:05 ` [Qemu-devel] [PATCH 06/10] pci: add storage class for sata Alexander Graf
@ 2010-11-17 1:05 ` Alexander Graf
2010-11-17 1:05 ` [Qemu-devel] [PATCH 08/10] ahci: add ahci emulation Alexander Graf
` (2 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Alexander Graf @ 2010-11-17 1:05 UTC (permalink / raw)
To: QEMU-devel Developers; +Cc: tj, Joerg Roedel, Sebastian Herbszt, Roland Elek
We need a PCI ID for our new AHCI adapter. I just picked an ICH-7M
because that's the one built into the first Macbooks.
This patch adds a PCI ID define for an ICH-7M AHCI adapter.
Signed-off-by: Alexander Graf <agraf@suse.de>
---
hw/pci.h | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/hw/pci.h b/hw/pci.h
index 7100804..be0f9c2 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -62,6 +62,7 @@
/* Intel (0x8086) */
#define PCI_DEVICE_ID_INTEL_82551IT 0x1209
#define PCI_DEVICE_ID_INTEL_82557 0x1229
+#define PCI_DEVICE_ID_INTEL_ICH7M_AHCI 0x27c5
/* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
#define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
--
1.6.0.2
^ permalink raw reply related [flat|nested] 18+ messages in thread* [Qemu-devel] [PATCH 08/10] ahci: add ahci emulation
2010-11-17 1:05 [Qemu-devel] [PATCH 00/10] AHCI emulation support Alexander Graf
` (6 preceding siblings ...)
2010-11-17 1:05 ` [Qemu-devel] [PATCH 07/10] pci: add ich7 pci id Alexander Graf
@ 2010-11-17 1:05 ` Alexander Graf
2010-11-17 9:08 ` Gerd Hoffmann
2010-11-17 1:05 ` [Qemu-devel] [PATCH 09/10] ahci: add -drive support Alexander Graf
2010-11-17 1:05 ` [Qemu-devel] [PATCH 10/10] ahci: spawn controller on demand Alexander Graf
9 siblings, 1 reply; 18+ messages in thread
From: Alexander Graf @ 2010-11-17 1:05 UTC (permalink / raw)
To: QEMU-devel Developers; +Cc: tj, Joerg Roedel, Sebastian Herbszt, Roland Elek
This patch adds an emulation layer for an ICH-7M AHCI controller. For now
this controller does not do IDE legacy emulation. It is a pure AHCI controller.
Signed-off-by: Alexander Graf <agraf@suse.de>
---
Makefile.objs | 1 +
Makefile.target | 4 +
default-configs/i386-softmmu.mak | 1 +
default-configs/x86_64-softmmu.mak | 1 +
hw/ahci.c | 1171 ++++++++++++++++++++++++++++++++++++
5 files changed, 1178 insertions(+), 0 deletions(-)
create mode 100644 hw/ahci.c
diff --git a/Makefile.objs b/Makefile.objs
index 15569af..8dfcefa 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -229,6 +229,7 @@ hw-obj-$(CONFIG_IDE_PIIX) += ide/piix.o
hw-obj-$(CONFIG_IDE_CMD646) += ide/cmd646.o
hw-obj-$(CONFIG_IDE_MACIO) += ide/macio.o
hw-obj-$(CONFIG_IDE_VIA) += ide/via.o
+hw-obj-$(CONFIG_AHCI) += ahci.o
# SCSI layer
hw-obj-y += lsi53c895a.o
diff --git a/Makefile.target b/Makefile.target
index 91e6e74..bd899cd 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -195,6 +195,10 @@ obj-y += e1000.o
# Inter-VM PCI shared memory
obj-$(CONFIG_KVM) += ivshmem.o
+# ahci
+#
+obj-$(CONFIG_AHCI) += ahci.o
+
# Hardware support
obj-i386-y += vga.o
obj-i386-y += mc146818rtc.o i8259.o pc.o
diff --git a/default-configs/i386-softmmu.mak b/default-configs/i386-softmmu.mak
index ed00471..66b92af 100644
--- a/default-configs/i386-softmmu.mak
+++ b/default-configs/i386-softmmu.mak
@@ -19,6 +19,7 @@ CONFIG_IDE_QDEV=y
CONFIG_IDE_PCI=y
CONFIG_IDE_ISA=y
CONFIG_IDE_PIIX=y
+CONFIG_AHCI=y
CONFIG_NE2000_ISA=y
CONFIG_PIIX_PCI=y
CONFIG_SOUND=y
diff --git a/default-configs/x86_64-softmmu.mak b/default-configs/x86_64-softmmu.mak
index 5183203..508e843 100644
--- a/default-configs/x86_64-softmmu.mak
+++ b/default-configs/x86_64-softmmu.mak
@@ -19,6 +19,7 @@ CONFIG_IDE_QDEV=y
CONFIG_IDE_PCI=y
CONFIG_IDE_ISA=y
CONFIG_IDE_PIIX=y
+CONFIG_AHCI=y
CONFIG_NE2000_ISA=y
CONFIG_PIIX_PCI=y
CONFIG_SOUND=y
diff --git a/hw/ahci.c b/hw/ahci.c
new file mode 100644
index 0000000..c892da1
--- /dev/null
+++ b/hw/ahci.c
@@ -0,0 +1,1171 @@
+/*
+ * QEMU AHCI Emulation
+ *
+ * Copyright (c) 2010 qiaochong@loongson.cn
+ * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com>
+ * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de>
+ * Copyright (c) 2010 Alexander Graf <agraf@suse.de>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+#include "hw.h"
+#include "monitor.h"
+#include "pci.h"
+#include "dma.h"
+#include "cpu-common.h"
+#include "scsi-defs.h"
+#include "scsi.h"
+#include "blockdev.h"
+#include <hw/ide/internal.h>
+#include <hw/ide/pci.h>
+
+/* #define DEBUG_AHCI */
+
+#ifdef DEBUG_AHCI
+#define DPRINTF(fmt, ...) \
+do { fprintf(stderr,"ahci: " fmt , ## __VA_ARGS__); } while (0)
+#else
+#define DPRINTF(fmt, ...) do {} while(0)
+#endif
+
+#define AHCI_PCI_BAR 5
+#define AHCI_MAX_PORTS 32
+#define AHCI_MAX_SG 168 /* hardware max is 64K */
+#define AHCI_DMA_BOUNDARY 0xffffffff
+#define AHCI_USE_CLUSTERING 0
+#define AHCI_MAX_CMDS 32
+#define AHCI_CMD_SZ 32
+#define AHCI_CMD_SLOT_SZ (AHCI_MAX_CMDS * AHCI_CMD_SZ)
+#define AHCI_RX_FIS_SZ 256
+#define AHCI_CMD_TBL_CDB 0x40
+#define AHCI_CMD_TBL_HDR_SZ 0x80
+#define AHCI_CMD_TBL_SZ (AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16))
+#define AHCI_CMD_TBL_AR_SZ (AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS)
+#define AHCI_PORT_PRIV_DMA_SZ (AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + \
+ AHCI_RX_FIS_SZ)
+
+#define AHCI_IRQ_ON_SG (1 << 31)
+#define AHCI_CMD_ATAPI (1 << 5)
+#define AHCI_CMD_WRITE (1 << 6)
+#define AHCI_CMD_PREFETCH (1 << 7)
+#define AHCI_CMD_RESET (1 << 8)
+#define AHCI_CMD_CLR_BUSY (1 << 10)
+
+#define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */
+#define RX_FIS_SDB 0x58 /* offset of SDB FIS data */
+#define RX_FIS_UNK 0x60 /* offset of Unknown FIS data */
+
+/* global controller registers */
+#define HOST_CAP 0x00 /* host capabilities */
+#define HOST_CTL 0x04 /* global host control */
+#define HOST_IRQ_STAT 0x08 /* interrupt status */
+#define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */
+#define HOST_VERSION 0x10 /* AHCI spec. version compliancy */
+
+/* HOST_CTL bits */
+#define HOST_CTL_RESET (1 << 0) /* reset controller; self-clear */
+#define HOST_CTL_IRQ_EN (1 << 1) /* global IRQ enable */
+#define HOST_CTL_AHCI_EN (1 << 31) /* AHCI enabled */
+
+/* HOST_CAP bits */
+#define HOST_CAP_SSC (1 << 14) /* Slumber capable */
+#define HOST_CAP_AHCI (1 << 18) /* AHCI only */
+#define HOST_CAP_CLO (1 << 24) /* Command List Override support */
+#define HOST_CAP_SSS (1 << 27) /* Staggered Spin-up */
+#define HOST_CAP_NCQ (1 << 30) /* Native Command Queueing */
+#define HOST_CAP_64 (1 << 31) /* PCI DAC (64-bit DMA) support */
+
+/* registers for each SATA port */
+#define PORT_LST_ADDR 0x00 /* command list DMA addr */
+#define PORT_LST_ADDR_HI 0x04 /* command list DMA addr hi */
+#define PORT_FIS_ADDR 0x08 /* FIS rx buf addr */
+#define PORT_FIS_ADDR_HI 0x0c /* FIS rx buf addr hi */
+#define PORT_IRQ_STAT 0x10 /* interrupt status */
+#define PORT_IRQ_MASK 0x14 /* interrupt enable/disable mask */
+#define PORT_CMD 0x18 /* port command */
+#define PORT_TFDATA 0x20 /* taskfile data */
+#define PORT_SIG 0x24 /* device TF signature */
+#define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */
+#define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */
+#define PORT_SCR_ERR 0x30 /* SATA phy register: SError */
+#define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */
+#define PORT_CMD_ISSUE 0x38 /* command issue */
+#define PORT_RESERVED 0x3c /* reserved */
+
+/* PORT_IRQ_{STAT,MASK} bits */
+#define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */
+#define PORT_IRQ_TF_ERR (1 << 30) /* task file error */
+#define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */
+#define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */
+#define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */
+#define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */
+#define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */
+#define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */
+
+#define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */
+#define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */
+#define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */
+#define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */
+#define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */
+#define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */
+#define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */
+#define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */
+#define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */
+
+#define PORT_IRQ_FREEZE (PORT_IRQ_HBUS_ERR | PORT_IRQ_IF_ERR | \
+ PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY | \
+ PORT_IRQ_UNK_FIS)
+#define PORT_IRQ_ERROR (PORT_IRQ_FREEZE | PORT_IRQ_TF_ERR | \
+ PORT_IRQ_HBUS_DATA_ERR)
+#define DEF_PORT_IRQ (PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | \
+ PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | \
+ PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS)
+
+/* PORT_CMD bits */
+#define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */
+#define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */
+#define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */
+#define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */
+#define PORT_CMD_CLO (1 << 3) /* Command list override */
+#define PORT_CMD_POWER_ON (1 << 2) /* Power up device */
+#define PORT_CMD_SPIN_UP (1 << 1) /* Spin up device */
+#define PORT_CMD_START (1 << 0) /* Enable port DMA engine */
+
+#define PORT_CMD_ICC_MASK (0xf << 28) /* i/f ICC state mask */
+#define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */
+#define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */
+#define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */
+
+#define PORT_IRQ_STAT_DHRS (1 << 0) /* Device to Host Register FIS */
+#define PORT_IRQ_STAT_PSS (1 << 1) /* PIO Setup FIS */
+#define PORT_IRQ_STAT_DSS (1 << 2) /* DMA Setup FIS */
+#define PORT_IRQ_STAT_SDBS (1 << 3) /* Set Device Bits */
+#define PORT_IRQ_STAT_UFS (1 << 4) /* Unknown FIS */
+#define PORT_IRQ_STAT_DPS (1 << 5) /* Descriptor Processed */
+#define PORT_IRQ_STAT_PCS (1 << 6) /* Port Connect Change Status */
+#define PORT_IRQ_STAT_DMPS (1 << 7) /* Device Mechanical Presence
+ Status */
+#define PORT_IRQ_STAT_PRCS (1 << 22) /* File Ready Status */
+#define PORT_IRQ_STAT_IPMS (1 << 23) /* Incorrect Port Multiplier
+ Status */
+#define PORT_IRQ_STAT_OFS (1 << 24) /* Overflow Status */
+#define PORT_IRQ_STAT_INFS (1 << 26) /* Interface Non-Fatal Error
+ Status */
+#define PORT_IRQ_STAT_IFS (1 << 27) /* Interface Fatal Error */
+#define PORT_IRQ_STAT_HBDS (1 << 28) /* Host Bus Data Error Status */
+#define PORT_IRQ_STAT_HBFS (1 << 29) /* Host Bus Fatal Error Status */
+#define PORT_IRQ_STAT_TFES (1 << 30) /* Task File Error Status */
+#define PORT_IRQ_STAT_CPDS (1 << 31) /* Code Port Detect Status */
+
+/* ap->flags bits */
+#define AHCI_FLAG_NO_NCQ (1 << 24)
+#define AHCI_FLAG_IGN_IRQ_IF_ERR (1 << 25) /* ignore IRQ_IF_ERR */
+#define AHCI_FLAG_HONOR_PI (1 << 26) /* honor PORTS_IMPL */
+#define AHCI_FLAG_IGN_SERR_INTERNAL (1 << 27) /* ignore SERR_INTERNAL */
+#define AHCI_FLAG_32BIT_ONLY (1 << 28) /* force 32bit */
+
+#define ATA_SRST (1 << 2) /* software reset */
+
+#define STATE_RUN 0
+#define STATE_RESET 1
+
+#define SATA_SCR_SSTATUS_DET_NODEV 0x0
+#define SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP 0x3
+
+#define SATA_SCR_SSTATUS_SPD_NODEV 0x00
+#define SATA_SCR_SSTATUS_SPD_GEN1 0x10
+
+#define SATA_SCR_SSTATUS_IPM_NODEV 0x000
+#define SATA_SCR_SSTATUS_IPM_ACTIVE 0X100
+
+#define AHCI_SCR_SCTL_DET 0xf
+
+#define SATA_FIS_TYPE_REGISTER_H2D 0x27
+#define SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER 0x80
+
+#define AHCI_CMD_HDR_CMD_FIS_LEN 0x1f
+#define AHCI_CMD_HDR_PRDT_LEN 16
+
+#define SATA_SIGNATURE_CDROM 0xeb140000
+#define SATA_SIGNATURE_DISK 0x00000101
+
+#define AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR 0x20
+ /* Shouldn't this be 0x2c? */
+
+#define SATA_PORTS 4
+
+#define AHCI_PORT_REGS_START_ADDR 0x100
+#define AHCI_PORT_REGS_END_ADDR (AHCI_PORT_REGS_START_ADDR + SATA_PORTS * 0x80)
+#define AHCI_PORT_ADDR_OFFSET_MASK 0x7f
+
+#define AHCI_NUM_COMMAND_SLOTS 31
+#define AHCI_SUPPORTED_SPEED 20
+#define AHCI_SUPPORTED_SPEED_GEN1 1
+#define AHCI_VERSION_1_0 0x10000
+
+#define AHCI_PROGMODE_MAJOR_REV_1 1
+
+#define AHCI_COMMAND_TABLE_ACMD 0x40
+
+#define IDE_FEATURE_DMA 1
+
+#define READ_FPDMA_QUEUED 0x60
+#define WRITE_FPDMA_QUEUED 0x61
+
+#define RES_FIS_DSFIS 0x00
+#define RES_FIS_PSFIS 0x20
+#define RES_FIS_RFIS 0x40
+#define RES_FIS_SDBFIS 0x58
+#define RES_FIS_UFIS 0x60
+
+typedef struct AHCIControlRegs {
+ uint32_t cap;
+ uint32_t ghc;
+ uint32_t irqstatus;
+ uint32_t impl;
+ uint32_t version;
+} __attribute__ ((packed)) AHCIControlRegs;
+
+typedef struct AHCIPortRegs {
+ uint32_t lst_addr;
+ uint32_t lst_addr_hi;
+ uint32_t fis_addr;
+ uint32_t fis_addr_hi;
+ uint32_t irq_stat;
+ uint32_t irq_mask;
+ uint32_t cmd;
+ uint32_t unused0;
+ uint32_t tfdata;
+ uint32_t sig;
+ uint32_t scr_stat;
+ uint32_t scr_ctl;
+ uint32_t scr_err;
+ uint32_t scr_act;
+ uint32_t cmd_issue;
+ uint32_t reserved;
+} __attribute__ ((packed)) AHCIPortRegs;
+
+typedef struct AHCICmdHdr {
+ uint32_t opts;
+ uint32_t status;
+ uint64_t tbl_addr;
+ uint32_t reserved[4];
+} __attribute__ ((packed)) AHCICmdHdr;
+
+typedef struct AHCI_SG {
+ uint32_t addr;
+ uint32_t addr_hi;
+ uint32_t reserved;
+ uint32_t flags_size;
+} __attribute__ ((packed)) AHCI_SG;
+
+typedef struct AHCIDevice AHCIDevice;
+
+struct AHCIDevice {
+ IDEBus port;
+ BMDMAState bmdma;
+ int connected;
+ int port_no;
+ uint32_t port_state;
+ uint32_t finished;
+ AHCIPortRegs port_regs;
+ struct AHCIState *hba;
+ uint8_t *lst;
+ uint8_t *res_fis;
+ AHCICmdHdr *cur_cmd;
+};
+
+typedef struct NCQTransferState {
+ AHCIDevice *drive;
+ QEMUSGList sglist;
+ int is_read;
+ uint16_t sector_count;
+ uint64_t lba;
+ uint8_t tag;
+ uint8_t *cmd_fis;
+ int cmd_fis_len;
+ int slot;
+ int used;
+} NCQTransferState;
+
+typedef struct AHCIState{
+ AHCIDevice dev[SATA_PORTS];
+ AHCIControlRegs control_regs;
+ int mem;
+ qemu_irq irq;
+ NCQTransferState ncq_tfs[AHCI_MAX_CMDS];
+} AHCIState;
+
+typedef struct AHCIPciState {
+ PCIDevice card;
+ AHCIState *ahci;
+} AHCIPciState;
+
+typedef struct H2D_NCQ_FIS {
+ uint8_t fis_type;
+ uint8_t c;
+ uint8_t command;
+ uint8_t sector_count_low;
+ uint8_t lba0;
+ uint8_t lba1;
+ uint8_t lba2;
+ uint8_t fua;
+ uint8_t lba3;
+ uint8_t lba4;
+ uint8_t lba5;
+ uint8_t sector_count_high;
+ uint8_t tag;
+ uint8_t reserved5;
+ uint8_t reserved6;
+ uint8_t control;
+ uint8_t reserved7;
+ uint8_t reserved8;
+ uint8_t reserved9;
+ uint8_t reserved10;
+} __attribute__ ((packed)) H2D_NCQ_FIS;
+
+static void ahci_transfer_start(IDEState *s, uint8_t *buf, int size,
+ EndTransferFunc *end_transfer_func);
+static void ahci_irq_set_fn(IDEBus *s);
+
+static void check_cmd(AHCIState *s, int port);
+static int handle_cmd(AHCIState *s,int port,int slot);
+static void ahci_reset_port(AHCIState *s, int port);
+static void ahci_write_fis_d2h(AHCIState *s, int port, uint8_t *cmd_fis);
+
+static uint32_t ahci_port_read(AHCIState *s, int port, int offset)
+{
+ uint32_t val;
+ uint32_t *p;
+ AHCIPortRegs *pr;
+ pr = &s->dev[port].port_regs;
+
+ switch (offset) {
+ case PORT_SCR_STAT:
+ if (s->dev[port].connected) {
+ val = SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP |
+ SATA_SCR_SSTATUS_SPD_GEN1 | SATA_SCR_SSTATUS_IPM_ACTIVE;
+ } else {
+ val = SATA_SCR_SSTATUS_DET_NODEV;
+ }
+ break;
+ case PORT_IRQ_STAT:
+ val = pr->irq_stat;
+ break;
+ case PORT_CMD_ISSUE:
+ val = 0;
+ break;
+ case PORT_SCR_ACT:
+ pr->scr_act &= ~s->dev[port].finished;
+ s->dev[port].finished = 0;
+ val = pr->scr_act;
+ break;
+ case PORT_TFDATA:
+ case PORT_SIG:
+ case PORT_SCR_CTL:
+ case PORT_SCR_ERR:
+ default:
+ p = (uint32_t *)&s->dev[port].port_regs;
+ val = p[offset / sizeof(*p)];
+ break;
+ }
+ DPRINTF("ahci_port_read: port: 0x%x offset: 0x%x val: 0x%x\n",
+ port, offset, val);
+ return val;
+
+}
+
+static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d,
+ int irq_type)
+{
+ DPRINTF("%s: trigger irq %#x -> %x\n", __FUNCTION__,
+ irq_type, d->port_regs.irq_mask & irq_type);
+
+ d->port_regs.irq_stat |= irq_type;
+
+ /* Only trigger an interrupt if unmasked */
+ if (d->port_regs.irq_mask & irq_type) {
+ s->control_regs.irqstatus |= (1 << d->port_no);
+ if (s->control_regs.ghc & HOST_CTL_IRQ_EN) {
+ qemu_irq_raise(s->irq);
+ }
+ }
+}
+
+static void ahci_check_irq(AHCIState *s)
+{
+ DPRINTF("%s: check irq %#x\n", __FUNCTION__,
+ s->control_regs.irqstatus);
+
+ if (s->control_regs.irqstatus &&
+ (s->control_regs.ghc & HOST_CTL_IRQ_EN)) {
+ qemu_irq_raise(s->irq);
+ }
+}
+
+static void map_page(uint8_t **ptr, uint64_t addr)
+{
+ target_phys_addr_t len = 4096;
+
+ if (*ptr) {
+ cpu_physical_memory_unmap(*ptr, 1, len, len);
+ }
+
+ *ptr = cpu_physical_memory_map(addr, &len, 1);
+ if (len < 4096) {
+ *ptr = NULL;
+ }
+}
+
+static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val)
+{
+ AHCIPortRegs *pr = &s->dev[port].port_regs;
+ uint32_t *p;
+
+ DPRINTF("ahci_port_write: port: 0x%x offset: 0x%x val: 0x%x\n",
+ port, offset, val);
+ switch (offset) {
+ case PORT_LST_ADDR:
+ pr->lst_addr = val;
+ map_page(&s->dev[port].lst,
+ ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr);
+ break;
+ case PORT_LST_ADDR_HI:
+ pr->lst_addr_hi = val;
+ map_page(&s->dev[port].lst,
+ ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr);
+ break;
+ case PORT_FIS_ADDR:
+ pr->fis_addr = val;
+ map_page(&s->dev[port].res_fis,
+ ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr);
+ break;
+ case PORT_FIS_ADDR_HI:
+ pr->fis_addr_hi = val;
+ map_page(&s->dev[port].res_fis,
+ ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr);
+ break;
+ case PORT_IRQ_STAT:
+ pr->irq_stat &= ~val;
+ break;
+ case PORT_IRQ_MASK:
+ pr->irq_mask = val & 0xfdc000ff;
+ break;
+ case PORT_CMD:
+ pr->cmd = val & ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON);
+
+ if (pr->cmd & PORT_CMD_START) {
+ pr->cmd |= PORT_CMD_LIST_ON;
+ }
+
+ if (pr->cmd & PORT_CMD_FIS_RX) {
+ pr->cmd |= PORT_CMD_FIS_ON;
+ }
+
+ check_cmd(s, port);
+ break;
+ case PORT_CMD_ISSUE:
+ pr->cmd_issue |= val;
+ check_cmd(s, port);
+ break;
+ case PORT_SCR_ERR:
+ pr->scr_err &= ~val;
+ break;
+ case PORT_SCR_ACT:
+ /* RW1 */
+ pr->scr_act |= val;
+ break;
+ case PORT_SCR_CTL:
+ if (((pr->scr_ctl & AHCI_SCR_SCTL_DET) == 1) &&
+ ((val & AHCI_SCR_SCTL_DET) == 0)) {
+ ahci_reset_port(s, port);
+ }
+ pr->scr_ctl = val;
+ break;
+ case PORT_TFDATA:
+ case PORT_SIG:
+ case PORT_SCR_STAT:
+ default:
+ p = (uint32_t *)pr;
+ p[offset / sizeof(*p)] = val;
+ break;
+ }
+
+}
+
+static uint32_t ahci_mem_readl(void *ptr, target_phys_addr_t addr)
+{
+ AHCIState *s = ptr;
+ uint32_t val;
+ uint32_t *p;
+ addr = addr & 0xfff;
+ if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) {
+ switch (addr) {
+ case HOST_IRQ_STAT:
+ default:
+ /* genernal host control */
+ p = (uint32_t *)&s->control_regs;
+ val = p[addr / sizeof(*p)];
+ }
+ } else if((addr >= AHCI_PORT_REGS_START_ADDR) &&
+ (addr < AHCI_PORT_REGS_END_ADDR)) {
+ val = ahci_port_read(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7,
+ addr & AHCI_PORT_ADDR_OFFSET_MASK);
+ } else {
+ val = 0;
+ }
+
+ DPRINTF("ahci_mem_readl: (addr 0x%08X), val 0x%08X\n",
+ (unsigned) addr, val);
+
+ return val;
+}
+
+
+
+static void ahci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
+{
+ AHCIState *s = ptr;
+ addr = addr & 0xfff;
+ int i;
+
+ /* Only aligned reads are allowed on AHCI */
+ if (addr & 3) {
+ fprintf(stderr, "ahci: Mis-aligned write to addr 0x"
+ TARGET_FMT_plx "\n", addr);
+ return;
+ }
+
+ if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) {
+ switch (addr) {
+ case HOST_CAP: /* R/WO, RO */
+ /* FIXME handle R/WO */
+ break;
+ case HOST_CTL: /* R/W */
+ if (val & HOST_CTL_RESET) {
+ DPRINTF("HBA Reset\n");
+ /* FIXME reset? */
+ } else {
+ s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN;
+ ahci_check_irq(s);
+ }
+ break;
+ case HOST_IRQ_STAT: /* R/WC, RO */
+ s->control_regs.irqstatus &= ~val;
+ for (i = 0; i < SATA_PORTS; i++) {
+ if (s->dev[i].port_regs.irq_stat) {
+ s->control_regs.irqstatus |= (1 << i);
+ qemu_irq_lower(s->irq);
+ qemu_irq_raise(s->irq);
+ }
+ }
+ if (!s->control_regs.irqstatus) {
+ qemu_irq_lower(s->irq);
+ }
+ break;
+ case HOST_PORTS_IMPL: /* R/WO, RO */
+ /* FIXME handle R/WO */
+ break;
+ case HOST_VERSION: /* RO */
+ /* FIXME report write? */
+ break;
+ default:
+ DPRINTF("write to unknown register 0x%x\n", (unsigned)addr);
+ }
+ } else if((addr >= AHCI_PORT_REGS_START_ADDR) &&
+ (addr < AHCI_PORT_REGS_END_ADDR)) {
+ ahci_port_write(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7,
+ addr & AHCI_PORT_ADDR_OFFSET_MASK, val);
+ }
+
+ DPRINTF("ahci_mem_writel: (addr 0x%08X), val 0x%08X\n",
+ (unsigned) addr, val);
+
+}
+
+static CPUReadMemoryFunc *ahci_readfn[3]={
+ ahci_mem_readl,
+ ahci_mem_readl,
+ ahci_mem_readl
+};
+
+static CPUWriteMemoryFunc *ahci_writefn[3]={
+ ahci_mem_writel,
+ ahci_mem_writel,
+ ahci_mem_writel
+};
+
+static void ahci_reg_init(AHCIState *s)
+{
+ int i;
+
+ s->control_regs.cap = (SATA_PORTS - 1) |
+ (AHCI_NUM_COMMAND_SLOTS << 8) |
+ (AHCI_SUPPORTED_SPEED_GEN1 << AHCI_SUPPORTED_SPEED) |
+ HOST_CAP_NCQ | HOST_CAP_AHCI;
+
+ s->control_regs.impl = (1 << SATA_PORTS) - 1;
+
+ s->control_regs.version = AHCI_VERSION_1_0;
+
+ for (i = 0; i < SATA_PORTS; i++) {
+ s->dev[i].port_state = STATE_RUN;
+ }
+}
+
+#ifndef min
+#define min(a, b) ((a) < (b) ? (a) : (b))
+#endif
+
+static uint32_t write_to_sglist(uint8_t *buffer, uint32_t len,
+ QEMUSGList *sglist)
+{
+ uint32_t i = 0;
+ uint32_t total = 0, once;
+ ScatterGatherEntry *cur_prd;
+ uint32_t sgcount;
+
+ cur_prd = sglist->sg;
+ sgcount = sglist->nsg;
+ for (i = 0; len && sgcount; i++) {
+ once = min(cur_prd->len + 1, len);
+ cpu_physical_memory_write(cur_prd->base, buffer, once);
+ cur_prd++;
+ sgcount--;
+ len -= once;
+ buffer += once;
+ total += once;
+ }
+
+ return total;
+}
+
+static void check_cmd(AHCIState *s, int port)
+{
+ AHCIPortRegs *pr = &s->dev[port].port_regs;
+ int slot;
+
+ if (pr->cmd & PORT_CMD_START) {
+ for (slot = 0; (slot < 32) && pr->cmd_issue; slot++) {
+ if ((pr->cmd_issue & (1 << slot)) &&
+ !handle_cmd(s, port, slot)) {
+ pr->cmd_issue &= ~(1 << slot);
+ }
+ }
+ }
+}
+
+static void ahci_reset_port(AHCIState *s, int port)
+{
+ IDEState *ide_state;
+ uint8_t init_fis[0x20];
+ uint32_t tfd;
+
+ if (!s->dev[port].connected) {
+ return;
+ }
+
+ DPRINTF("%s: reset\n", __FUNCTION__);
+
+ memset(init_fis, 0, sizeof(init_fis));
+ ide_state = &s->dev[port].port.ifs[0];
+ s->dev[port].port_state = STATE_RUN;
+ if (bdrv_get_type_hint(ide_state->bs) == BDRV_TYPE_CDROM) {
+ s->dev[port].port_regs.sig = SATA_SIGNATURE_CDROM;
+ init_fis[5] = 0x14;
+ init_fis[6] = 0xeb;
+ tfd = (1 << 8) | SEEK_STAT | WRERR_STAT | READY_STAT;
+ } else {
+ s->dev[port].port_regs.sig = SATA_SIGNATURE_DISK;
+ tfd = (1 << 8) | SEEK_STAT | WRERR_STAT;
+ }
+
+ ide_state->error = 1;
+ ide_state->status = 0;
+ init_fis[4] = 1;
+ init_fis[12] = 1;
+ ahci_write_fis_d2h(s, port, init_fis);
+
+ s->dev[port].port_regs.tfdata = tfd;
+}
+
+static void debug_print_fis(uint8_t *fis, int cmd_len)
+{
+#ifdef DEBUG_AHCI
+ int i;
+
+ fprintf(stderr, "fis:");
+ for (i = 0; i < cmd_len; i++) {
+ if ((i & 0xf) == 0) {
+ fprintf(stderr, "\n%02x:",i);
+ }
+ fprintf(stderr, "%02x ",fis[i]);
+ }
+ fprintf(stderr, "\n");
+#endif
+}
+
+static void ahci_write_fis_sdb(AHCIState *s, int port, uint32_t finished)
+{
+ AHCIPortRegs *pr = &s->dev[port].port_regs;
+ IDEState *ide_state;
+ uint8_t *sdb_fis;
+
+ if (!s->dev[port].res_fis ||
+ !(pr->cmd & PORT_CMD_FIS_RX)) {
+ return;
+ }
+
+ sdb_fis = &s->dev[port].res_fis[RES_FIS_SDBFIS];
+ ide_state = &s->dev[port].port.ifs[0];
+
+ pr->tfdata = (uint16_t)ide_state->error << 8 | ide_state->status;
+
+ /* clear memory */
+ *(uint32_t*)sdb_fis = 0;
+
+ /* write values */
+ sdb_fis[0] = ide_state->error;
+ sdb_fis[2] = ide_state->status & 0x77;
+ s->dev[port].finished |= finished;
+ *(uint32_t*)(sdb_fis + 4) = cpu_to_le32(s->dev[port].finished);
+
+ ahci_trigger_irq(s, &s->dev[port], PORT_IRQ_STAT_SDBS);
+}
+
+static void ahci_write_fis_d2h(AHCIState *s, int port, uint8_t *cmd_fis)
+{
+ AHCIPortRegs *pr = &s->dev[port].port_regs;
+ uint8_t *d2h_fis;
+ int i;
+
+ if (!s->dev[port].res_fis ||
+ !(pr->cmd & PORT_CMD_FIS_RX)) {
+ return;
+ }
+
+ d2h_fis = &s->dev[port].res_fis[RES_FIS_RFIS];
+
+ d2h_fis[0] = 0x34;
+ d2h_fis[1] = (s->control_regs.irqstatus ? (1 << 6) : 0);
+ d2h_fis[2] = s->dev[port].port.ifs[0].status;
+ d2h_fis[3] = s->dev[port].port.ifs[0].error;
+
+ d2h_fis[4] = cmd_fis[4];
+ d2h_fis[5] = cmd_fis[5];
+ d2h_fis[6] = cmd_fis[6];
+ d2h_fis[7] = cmd_fis[7];
+ d2h_fis[8] = cmd_fis[8];
+ d2h_fis[9] = cmd_fis[9];
+ d2h_fis[10] = cmd_fis[10];
+ d2h_fis[11] = cmd_fis[11];
+ d2h_fis[12] = cmd_fis[12];
+ d2h_fis[13] = cmd_fis[13];
+ for (i = 14; i < 0x20; i++) {
+ d2h_fis[i] = 0;
+ }
+
+ pr->tfdata = (uint16_t)d2h_fis[3] << 8 | d2h_fis[2];
+
+ if (d2h_fis[2] & ERR_STAT) {
+ ahci_trigger_irq(s, &s->dev[port], PORT_IRQ_STAT_TFES);
+ }
+
+ ahci_trigger_irq(s, &s->dev[port], PORT_IRQ_D2H_REG_FIS);
+}
+
+static void ncq_cb(void *opaque, int ret)
+{
+ NCQTransferState *ncq_tfs = (NCQTransferState *)opaque;
+ IDEState *ide_state;
+
+ if (ret < 0) {
+ /* error */
+ }
+
+ /* Clear bit for this tag in SActive */
+ ncq_tfs->drive->port_regs.scr_act &= ~(1 << ncq_tfs->tag);
+
+ ide_state = &ncq_tfs->drive->port.ifs[0];
+ ide_state->status = READY_STAT | SEEK_STAT;
+
+ /* XXX do we send a d2h fis here? */
+ ahci_write_fis_d2h(ncq_tfs->drive->hba, ncq_tfs->drive->port_no,
+ ncq_tfs->cmd_fis);
+
+ ahci_write_fis_sdb(ncq_tfs->drive->hba, ncq_tfs->drive->port_no,
+ (1 << ncq_tfs->tag));
+
+ DPRINTF("NCQ transfer tag %d finished\n", ncq_tfs->tag);
+
+ qemu_sglist_destroy(&ncq_tfs->sglist);
+ cpu_physical_memory_unmap(ncq_tfs->cmd_fis, 1, ncq_tfs->cmd_fis_len,
+ ncq_tfs->cmd_fis_len);
+
+ ncq_tfs->used = 0;
+}
+
+static void process_ncq_command(AHCIState *s, int port, uint8_t *cmd_fis,
+ int slot, QEMUSGList *sg)
+{
+ H2D_NCQ_FIS *ncq_fis = (H2D_NCQ_FIS*)cmd_fis;
+ uint8_t tag = ncq_fis->tag >> 3;
+ NCQTransferState *ncq_tfs = &s->ncq_tfs[tag];
+
+ if (ncq_tfs->used) {
+ /* error - already in use */
+ fprintf(stderr, "%s: tag %d already used\n", __FUNCTION__, tag);
+ return;
+ }
+
+ ncq_tfs->used = 1;
+ ncq_tfs->cmd_fis = cmd_fis;
+ ncq_tfs->cmd_fis_len = 0x20;
+ ncq_tfs->slot = slot;
+ ncq_tfs->lba = ((uint64_t)ncq_fis->lba5 << 40) |
+ ((uint64_t)ncq_fis->lba4 << 32) |
+ ((uint64_t)ncq_fis->lba3 << 24) |
+ ((uint64_t)ncq_fis->lba2 << 16) |
+ ((uint64_t)ncq_fis->lba1 << 8) |
+ (uint64_t)ncq_fis->lba0;
+
+ /* Note: We calculate the sector count, but don't currently rely on it.
+ * The total size of the DMA buffer tells us the transfer size instead. */
+ ncq_tfs->sector_count = ((uint16_t)ncq_fis->sector_count_high << 8) |
+ ncq_fis->sector_count_low;
+
+ DPRINTF("NCQ transfer LBA from %ld to %ld, drive max %ld\n",
+ ncq_tfs->lba, ncq_tfs->lba + ncq_tfs->sector_count - 2,
+ s->dev[port].port.ifs[0].nb_sectors - 1);
+
+ ncq_tfs->sglist = *sg;
+ ncq_tfs->drive = &s->dev[port];
+ ncq_tfs->tag = tag;
+
+ switch(ncq_fis->command) {
+ case READ_FPDMA_QUEUED:
+ DPRINTF("ahci: NCQ reading %d sectors from LBA %ld, tag %d\n",
+ ncq_tfs->sector_count-1, ncq_tfs->lba, ncq_tfs->tag);
+ ncq_tfs->is_read = 1;
+
+ /* XXX: The specification is unclear about whether the DMA Setup
+ * FIS here should have the I bit set, but it suggest that it should
+ * not. Linux works without this interrupt, so I disabled it.
+ * If someone knows if it is needed, please tell me, or fix this. */
+
+ /* ahci_trigger_irq(s,s->dev[port],PORT_IRQ_STAT_DSS); */
+ DPRINTF("tag %d aio read %ld\n", ncq_tfs->tag, ncq_tfs->lba);
+ dma_bdrv_read(ncq_tfs->drive->port.ifs[0].bs, &ncq_tfs->sglist,
+ ncq_tfs->lba, ncq_cb, ncq_tfs);
+ break;
+ case WRITE_FPDMA_QUEUED:
+ DPRINTF("ahci: NCQ writing %d sectors to LBA %ld, tag %d\n",
+ ncq_tfs->sector_count-1, ncq_tfs->lba, ncq_tfs->tag);
+ ncq_tfs->is_read = 0;
+ /* ahci_trigger_irq(s,s->dev[port],PORT_IRQ_STAT_DSS); */
+ DPRINTF("tag %d aio write %ld\n", ncq_tfs->tag, ncq_tfs->lba);
+ dma_bdrv_write(ncq_tfs->drive->port.ifs[0].bs, &ncq_tfs->sglist,
+ ncq_tfs->lba, ncq_cb, ncq_tfs);
+ break;
+ default:
+ hw_error("ahci: tried to process non-NCQ command as NCQ\n");
+ break;
+ }
+}
+
+static int handle_cmd(AHCIState *s, int port, int slot)
+{
+ IDEState *ide_state;
+
+ int sglist_alloc_hint;
+ QEMUSGList sglist;
+ int atapi_packet_len = 0;
+ AHCIPortRegs *pr;
+ uint32_t opts;
+ uint64_t tbl_addr;
+ AHCICmdHdr *cmd;
+ uint8_t *cmd_fis;
+
+ target_phys_addr_t cmd_len;
+ int i;
+
+ pr = &s->dev[port].port_regs;
+ cmd = (AHCICmdHdr *)&s->dev[port].lst[slot * 32];
+
+ if (!s->dev[port].lst) {
+ hw_error("%s: lst not given but cmd handled", __FUNCTION__);
+ }
+
+ opts = le32_to_cpu(cmd->opts);
+ tbl_addr = le64_to_cpu(cmd->tbl_addr);
+
+ cmd_len = (opts & AHCI_CMD_HDR_CMD_FIS_LEN) * 4;
+ cmd_fis = cpu_physical_memory_map(tbl_addr, &cmd_len, 1);
+
+ /* The device we are working for */
+ ide_state = &s->dev[port].port.ifs[0];
+
+ /* Get number of entries in the PRDT, init a qemu sglist accordingly */
+ sglist_alloc_hint = opts >> AHCI_CMD_HDR_PRDT_LEN;
+ memset(&sglist, 0, sizeof(sglist));
+
+ if (sglist_alloc_hint > 0) {
+ qemu_sglist_init(&sglist, sglist_alloc_hint);
+ /* Parse the PRDs and create qemu sglist entries accordingly */
+ for (i = 0; i < sglist_alloc_hint; i++) {
+ target_phys_addr_t cur_prd_addr;
+
+ cur_prd_addr = tbl_addr + 0x80 + i * sizeof(AHCI_SG);
+ /* flags_size is zero-based */
+ qemu_sglist_add(&sglist,
+ ldl_phys(cur_prd_addr + offsetof(AHCI_SG, addr)),
+ ldl_phys(cur_prd_addr + offsetof(AHCI_SG, flags_size)) + 1);
+ }
+ }
+
+ debug_print_fis(cmd_fis, cmd_len);
+
+ switch (cmd_fis[0]) {
+ case SATA_FIS_TYPE_REGISTER_H2D:
+ break;
+ default:
+ hw_error("unknown command cmd_fis[0]=%02x cmd_fis[1]=%02x cmd_fis[2]=%02x\n",
+ cmd_fis[0], cmd_fis[1], cmd_fis[2]);
+ break;
+ }
+
+ switch (cmd_fis[1]) {
+ case SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER:
+ break;
+ case 0:
+ break;
+ default:
+ hw_error("unknown command cmd_fis[0]=%02x cmd_fis[1]=%02x cmd_fis[2]=%02x\n",
+ cmd_fis[0], cmd_fis[1], cmd_fis[2]);
+ break;
+ }
+
+ switch (s->dev[port].port_state) {
+ case STATE_RUN:
+ if (cmd_fis[15] & ATA_SRST) {
+ s->dev[port].port_state = STATE_RESET;
+ }
+ break;
+ case STATE_RESET:
+ if (!(cmd_fis[15] & ATA_SRST)) {
+ ahci_reset_port(s, port);
+ }
+ break;
+ }
+
+ if (cmd_fis[1] == SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER) {
+
+ /* Check for NCQ command */
+ if ((cmd_fis[2] == READ_FPDMA_QUEUED) ||
+ (cmd_fis[2] == WRITE_FPDMA_QUEUED)) {
+ process_ncq_command(s, port, cmd_fis, slot, &sglist);
+ goto out;
+ }
+
+ /* If the command is not NCQ, the sglist is needed in the core */
+ ide_state->sg = sglist;
+
+ /* Decompose the FIS */
+ ide_state->nsector = (int64_t)((cmd_fis[13] << 8) | cmd_fis[12]);
+ if (!ide_state->nsector) {
+ ide_state->nsector = 256;
+ }
+ ide_set_sector(ide_state, (cmd_fis[6] << 16) | (cmd_fis[5] << 8) |
+ cmd_fis[4]);
+
+ /* Copy the ACMD field (ATAPI packet, if any) from the AHCI command
+ * table to ide_state->io_buffer
+ */
+ if (opts & AHCI_CMD_ATAPI) {
+ atapi_packet_len = ((ide_state->hcyl) << 8) + ide_state->lcyl;
+ cpu_physical_memory_read(tbl_addr + AHCI_COMMAND_TABLE_ACMD,
+ ide_state->io_buffer, 0x10);
+ }
+
+ ide_state->error = 0;
+ s->dev[port].cur_cmd = cmd;
+
+ /* We're ready to process the command in FIS byte 2. */
+ ide_exec_cmd(&s->dev[port].port, cmd_fis[2]);
+
+ ahci_write_fis_d2h(s, port, cmd_fis);
+ }
+
+out:
+ cpu_physical_memory_unmap(cmd_fis, 1, cmd_len, cmd_len);
+
+ return 0;
+}
+
+static void ahci_transfer_start(IDEState *s, uint8_t *buf, int size,
+ EndTransferFunc *end_transfer_func)
+{
+ AHCIDevice *ad;
+ AHCIState *as;
+
+ s->end_transfer_func = end_transfer_func;
+
+ ad = DO_UPCAST(AHCIDevice, port, s->bus);
+ as = ad->hba;
+
+ write_to_sglist(buf, (uint32_t)size, &s->sg);
+
+ if (!(s->status & ERR_STAT)) {
+ s->status |= DRQ_STAT;
+ }
+
+ /* update number of transferred bytes */
+ ad->cur_cmd->status = cpu_to_le32(size);
+ ide_data_readw(s->bus, 0); /* The second parameter is unused. */
+}
+
+static void ahci_dma_start_fn(IDEState *s, BlockDriverCompletionFunc *dma_cb)
+{
+ AHCIDevice *ad;
+ AHCIState *as;
+ BMDMAState *bm = s->bus->bmdma;
+
+ ad = DO_UPCAST(AHCIDevice, port, s->bus);
+ as = ad->hba;
+
+ if (!bm) {
+ return;
+ }
+
+ bm->unit = s->unit;
+ bm->dma_cb = dma_cb;
+ bm->cur_prd_last = 0;
+ bm->cur_prd_addr = 0;
+ bm->cur_prd_len = 0;
+ bm->sector_num = ide_get_sector(s);
+ bm->nsector = s->nsector;
+ bmdma_cmd_writeb(bm, 0, 1);
+}
+
+static void ahci_irq_set_fn(IDEBus *s)
+{
+ AHCIDevice *ad;
+ AHCIState *as;
+
+ ad = DO_UPCAST(AHCIDevice, port, s);
+ as = ad->hba;
+
+ /* error interrupts will be triggered later */
+ if (ad->port.ifs[0].status & ERR_STAT) {
+ return;
+ }
+
+ ahci_trigger_irq(as, ad, PORT_IRQ_STAT_DSS);
+}
+
+static AHCIState *ahci_new(void)
+{
+ int i;
+
+ AHCIState *s = qemu_mallocz(sizeof(AHCIState));
+ AHCIDevice *ad;
+ ahci_reg_init(s);
+ s->mem = cpu_register_io_memory(ahci_readfn, ahci_writefn, s);
+
+ for (i = 0; i < SATA_PORTS; i++) {
+ DriveInfo *dinfo = drive_get(IF_SATA, 0, i);
+
+ if (!dinfo) {
+ continue;
+ }
+
+ ad = &s->dev[i];
+ ide_init2_with_non_qdev_drives(&ad->port, dinfo, NULL, 0);
+ ad->connected = 1;
+ ad->hba = s;
+ ad->port_no = i;
+ ad->port.ifs[0].bus = &ad->port;
+ ad->port.bmdma = &ad->bmdma;
+ ad->bmdma.bus = &ad->port;
+
+ ad->port.extender.transfer_start_fn = ahci_transfer_start;
+ ad->port.extender.irq_set_fn = ahci_irq_set_fn;
+ ad->port.extender.dma_start_fn = ahci_dma_start_fn;
+
+ ad->port.ifs[0].feature |= IDE_FEATURE_DMA;
+ ad->port.ifs[0].sg_third_party = 1;
+ ad->port.ifs[0].ncq_queues = AHCI_MAX_CMDS;
+
+ ad->port_regs.cmd = PORT_CMD_SPIN_UP | PORT_CMD_POWER_ON;
+ }
+
+ return s;
+}
+
+static void ahci_pci_map(PCIDevice *pci_dev, int region_num,
+ pcibus_t addr, pcibus_t size, int type)
+{
+ struct AHCIPciState *d = (struct AHCIPciState *)pci_dev;
+ AHCIState *s = d->ahci;
+
+ cpu_register_physical_memory(addr, size, s->mem);
+}
+
+
+static int pci_ahci_init(PCIDevice *dev)
+{
+ struct AHCIPciState *d;
+ d = DO_UPCAST(struct AHCIPciState, card, dev);
+ pci_config_set_vendor_id(d->card.config, PCI_VENDOR_ID_INTEL);
+ pci_config_set_device_id(d->card.config, PCI_DEVICE_ID_INTEL_ICH7M_AHCI);
+ d->card.config[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
+ PCI_COMMAND_MASTER;
+
+ pci_config_set_class(d->card.config, PCI_CLASS_STORAGE_SATA);
+ pci_config_set_prog_interface(d->card.config, AHCI_PROGMODE_MAJOR_REV_1);
+
+ d->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */
+ d->card.config[PCI_LATENCY_TIMER] = 0x00; /* Latency timer */
+ d->card.config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL;
+ d->card.config[PCI_INTERRUPT_PIN] = 1; /* interrupt pin 0 */
+
+ pci_register_bar(&d->card, 5, 0x400, PCI_BASE_ADDRESS_SPACE_MEMORY,
+ ahci_pci_map);
+ d->ahci = ahci_new();
+ d->ahci->irq = d->card.irq[0];
+ return 0;
+}
+
+static int pci_ahci_uninit(PCIDevice *dev)
+{
+ return 0;
+}
+
+static PCIDeviceInfo ahci_info = {
+ .qdev.name = "ahci",
+ .qdev.size = sizeof(AHCIPciState),
+ .init = pci_ahci_init,
+ .exit = pci_ahci_uninit,
+ .qdev.props = (Property[]) {
+ DEFINE_PROP_END_OF_LIST(),
+ }
+};
+
+static void ahci_pci_register_devices(void)
+{
+ pci_qdev_register(&ahci_info);
+}
+
+device_init(ahci_pci_register_devices)
--
1.6.0.2
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [Qemu-devel] [PATCH 08/10] ahci: add ahci emulation
2010-11-17 1:05 ` [Qemu-devel] [PATCH 08/10] ahci: add ahci emulation Alexander Graf
@ 2010-11-17 9:08 ` Gerd Hoffmann
2010-11-17 12:21 ` Alexander Graf
0 siblings, 1 reply; 18+ messages in thread
From: Gerd Hoffmann @ 2010-11-17 9:08 UTC (permalink / raw)
To: Alexander Graf
Cc: tj, Joerg Roedel, Roland Elek, QEMU-devel Developers,
Sebastian Herbszt
Hi,
> +static AHCIState *ahci_new(void)
> +{
> + int i;
> +
> +static int pci_ahci_init(PCIDevice *dev)
> +{
> + d->ahci = ahci_new();
> + d->ahci->irq = d->card.irq[0];
> + return 0;
> +}
Hmm, no bus registered anywhere. Dunno whenever it makes sense to
register ide bus(es) here or whenever we should create a new sata bus.
cheers,
Gerd
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [Qemu-devel] [PATCH 08/10] ahci: add ahci emulation
2010-11-17 9:08 ` Gerd Hoffmann
@ 2010-11-17 12:21 ` Alexander Graf
2010-11-17 13:56 ` Gerd Hoffmann
0 siblings, 1 reply; 18+ messages in thread
From: Alexander Graf @ 2010-11-17 12:21 UTC (permalink / raw)
To: Gerd Hoffmann
Cc: tj, Joerg Roedel, Roland Elek, QEMU-devel Developers,
Sebastian Herbszt
On 17.11.2010, at 10:08, Gerd Hoffmann wrote:
> Hi,
>
>> +static AHCIState *ahci_new(void)
>> +{
>> + int i;
>> +
>
>> +static int pci_ahci_init(PCIDevice *dev)
>> +{
>
>> + d->ahci = ahci_new();
>> + d->ahci->irq = d->card.irq[0];
>> + return 0;
>> +}
>
> Hmm, no bus registered anywhere. Dunno whenever it makes sense to register ide bus(es) here or whenever we should create a new sata bus.
I'm not sure I understand this comment :).
Alex
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [Qemu-devel] [PATCH 08/10] ahci: add ahci emulation
2010-11-17 12:21 ` Alexander Graf
@ 2010-11-17 13:56 ` Gerd Hoffmann
0 siblings, 0 replies; 18+ messages in thread
From: Gerd Hoffmann @ 2010-11-17 13:56 UTC (permalink / raw)
To: Alexander Graf
Cc: tj, Joerg Roedel, Roland Elek, QEMU-devel Developers,
Sebastian Herbszt
Hi,
>> Hmm, no bus registered anywhere. Dunno whenever it makes sense to
>> register ide bus(es) here or whenever we should create a new sata
>> bus.
>
> I'm not sure I understand this comment :).
The ahci controller should register one or more busses where you can
hook up devices to via -device. Right now the code seems to use one ide
bus per sata port, with ide drives being attached to the master channel
only. The ide bus isn't registered though, so it isn't visible via
qdev. Thus you can't construct a machine with ahci using -device.
Also a ide bus as it works currently isn't exactly a good fit, there is
no such thing as master/slave in sata. Dunno whenever it is better to
create a new sata bus or to extend the current ide bus code so it can
handle both pata and sata.
Hope it is more clear now ;)
cheers,
Gerd
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH 09/10] ahci: add -drive support
2010-11-17 1:05 [Qemu-devel] [PATCH 00/10] AHCI emulation support Alexander Graf
` (7 preceding siblings ...)
2010-11-17 1:05 ` [Qemu-devel] [PATCH 08/10] ahci: add ahci emulation Alexander Graf
@ 2010-11-17 1:05 ` Alexander Graf
2010-11-17 1:05 ` [Qemu-devel] [PATCH 10/10] ahci: spawn controller on demand Alexander Graf
9 siblings, 0 replies; 18+ messages in thread
From: Alexander Graf @ 2010-11-17 1:05 UTC (permalink / raw)
To: QEMU-devel Developers; +Cc: tj, Joerg Roedel, Sebastian Herbszt, Roland Elek
We need to be able to spawn new AHCI drives, so let's add AHCI support
to the -drive option.
Signed-off-by: Alexander Graf <agraf@suse.de>
---
blockdev.c | 6 +++++-
blockdev.h | 1 +
qemu-common.h | 2 +-
3 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/blockdev.c b/blockdev.c
index 6cb179a..5ce90cc 100644
--- a/blockdev.c
+++ b/blockdev.c
@@ -209,6 +209,9 @@ DriveInfo *drive_init(QemuOpts *opts, int default_to_scsi, int *fatal_error)
} else if (!strcmp(buf, "xen")) {
type = IF_XEN;
max_devs = 0;
+ } else if (!strcmp(buf, "sata")) {
+ type = IF_SATA;
+ max_devs = MAX_SATA_DEVS;
} else if (!strcmp(buf, "none")) {
type = IF_NONE;
max_devs = 0;
@@ -402,7 +405,7 @@ DriveInfo *drive_init(QemuOpts *opts, int default_to_scsi, int *fatal_error)
} else {
/* no id supplied -> create one */
dinfo->id = qemu_mallocz(32);
- if (type == IF_IDE || type == IF_SCSI)
+ if (type == IF_IDE || type == IF_SCSI || type == IF_SATA)
mediastr = (media == MEDIA_CDROM) ? "-cd" : "-hd";
if (max_devs)
snprintf(dinfo->id, 32, "%s%i%s%i",
@@ -427,6 +430,7 @@ DriveInfo *drive_init(QemuOpts *opts, int default_to_scsi, int *fatal_error)
case IF_IDE:
case IF_SCSI:
case IF_XEN:
+ case IF_SATA:
case IF_NONE:
switch(media) {
case MEDIA_DISK:
diff --git a/blockdev.h b/blockdev.h
index 653affc..f50a15e 100644
--- a/blockdev.h
+++ b/blockdev.h
@@ -33,6 +33,7 @@ struct DriveInfo {
#define MAX_IDE_DEVS 2
#define MAX_SCSI_DEVS 7
+#define MAX_SATA_DEVS 4
DriveInfo *drive_get(BlockInterfaceType type, int bus, int unit);
int drive_get_max_bus(BlockInterfaceType type);
diff --git a/qemu-common.h b/qemu-common.h
index b3957f1..ae1cfca 100644
--- a/qemu-common.h
+++ b/qemu-common.h
@@ -257,7 +257,7 @@ typedef uint64_t pcibus_t;
typedef enum {
IF_NONE,
IF_IDE, IF_SCSI, IF_FLOPPY, IF_PFLASH, IF_MTD, IF_SD, IF_VIRTIO, IF_XEN,
- IF_COUNT
+ IF_SATA, IF_COUNT
} BlockInterfaceType;
void cpu_exec_init_all(unsigned long tb_size);
--
1.6.0.2
^ permalink raw reply related [flat|nested] 18+ messages in thread* [Qemu-devel] [PATCH 10/10] ahci: spawn controller on demand
2010-11-17 1:05 [Qemu-devel] [PATCH 00/10] AHCI emulation support Alexander Graf
` (8 preceding siblings ...)
2010-11-17 1:05 ` [Qemu-devel] [PATCH 09/10] ahci: add -drive support Alexander Graf
@ 2010-11-17 1:05 ` Alexander Graf
9 siblings, 0 replies; 18+ messages in thread
From: Alexander Graf @ 2010-11-17 1:05 UTC (permalink / raw)
To: QEMU-devel Developers; +Cc: tj, Joerg Roedel, Sebastian Herbszt, Roland Elek
When we add a device using -drive to the guest, we also need to create a
new SATA bus to handle the device. This patch does it the same way SCSI
does it today.
Signed-off-by: Alexander Graf <agraf@suse.de>
---
hw/pc.c | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/hw/pc.c b/hw/pc.c
index 69b13bf..d0320c4 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -1075,4 +1075,9 @@ void pc_pci_device_init(PCIBus *pci_bus)
for (bus = 0; bus <= max_bus; bus++) {
pci_create_simple(pci_bus, -1, "lsi53c895a");
}
+
+ max_bus = drive_get_max_bus(IF_SATA);
+ for (bus = 0; bus <= max_bus; bus++) {
+ pci_create_simple(pci_bus, -1, "ahci");
+ }
}
--
1.6.0.2
^ permalink raw reply related [flat|nested] 18+ messages in thread