From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=51230 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PKy0A-00046a-AG for qemu-devel@nongnu.org; Tue, 23 Nov 2010 13:54:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PKy08-00079S-Nl for qemu-devel@nongnu.org; Tue, 23 Nov 2010 13:54:02 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:30450) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PKy08-000780-Gq for qemu-devel@nongnu.org; Tue, 23 Nov 2010 13:54:00 -0500 From: Peter Maydell Date: Tue, 23 Nov 2010 18:53:51 +0000 Message-Id: <1290538431-13170-13-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1290538431-13170-1-git-send-email-peter.maydell@linaro.org> References: <1290538431-13170-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 12/12] ARM: fix ldrexd/strexd List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori , qemu-devel@nongnu.org Correct ldrexd and strexd code to always read and write the high word of the 64-bit value from addr+4. Also make ldrexd and strexd agree that for a 64 bit value the address in env->exclusive_addr is that of the low word. This fixes the issues reported in https://bugs.launchpad.net/qemu/+bug/670883 Signed-off-by: Peter Maydell --- linux-user/main.c | 2 +- target-arm/translate.c | 8 +++++--- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/linux-user/main.c b/linux-user/main.c index dbba8be..274019f 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -589,7 +589,7 @@ static int do_strex(CPUARMState *env) } if (size == 3) { val = env->regs[(env->exclusive_info >> 12) & 0xf]; - segv = put_user_u32(val, addr); + segv = put_user_u32(val, addr + 4); if (segv) { env->cp15.c6_data = addr + 4; goto done; diff --git a/target-arm/translate.c b/target-arm/translate.c index f018653..fc1d399 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -5935,8 +5935,10 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2, tcg_gen_mov_i32(cpu_exclusive_val, tmp); store_reg(s, rt, tmp); if (size == 3) { - tcg_gen_addi_i32(addr, addr, 4); - tmp = gen_ld32(addr, IS_USER(s)); + TCGv tmp2 = new_tmp(); + tcg_gen_addi_i32(tmp2, addr, 4); + tmp = gen_ld32(tmp2, IS_USER(s)); + dead_tmp(tmp2); tcg_gen_mov_i32(cpu_exclusive_high, tmp); store_reg(s, rt2, tmp); } @@ -5996,7 +5998,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, if (size == 3) { TCGv tmp2 = new_tmp(); tcg_gen_addi_i32(tmp2, addr, 4); - tmp = gen_ld32(addr, IS_USER(s)); + tmp = gen_ld32(tmp2, IS_USER(s)); dead_tmp(tmp2); tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_high, fail_label); dead_tmp(tmp); -- 1.6.3.3