From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=45351 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PNeVG-0007Hq-Lv for qemu-devel@nongnu.org; Tue, 30 Nov 2010 23:41:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PNRJt-0002PB-HF for qemu-devel@nongnu.org; Tue, 30 Nov 2010 09:36:39 -0500 Received: from cantor2.suse.de ([195.135.220.15]:33256 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PNRJt-0001JP-7Q for qemu-devel@nongnu.org; Tue, 30 Nov 2010 09:36:37 -0500 From: Alexander Graf Date: Tue, 30 Nov 2010 15:35:56 +0100 Message-Id: <1291127761-16501-11-git-send-email-agraf@suse.de> In-Reply-To: <1291127761-16501-1-git-send-email-agraf@suse.de> References: <1291127761-16501-1-git-send-email-agraf@suse.de> Subject: [Qemu-devel] [PATCH 10/15] ppc4xx_pci: Declare as little endian List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: QEMU-devel Developers Cc: Blue Swirl , Paul Brook This patch replaces explicit bswaps with endianness hints to the mmio layer. Signed-off-by: Alexander Graf --- hw/ppc4xx_pci.c | 17 ++--------------- 1 files changed, 2 insertions(+), 15 deletions(-) diff --git a/hw/ppc4xx_pci.c b/hw/ppc4xx_pci.c index f2ecece..f62f1f9 100644 --- a/hw/ppc4xx_pci.c +++ b/hw/ppc4xx_pci.c @@ -24,7 +24,6 @@ #include "ppc4xx.h" #include "pci.h" #include "pci_host.h" -#include "bswap.h" #undef DEBUG #ifdef DEBUG @@ -102,10 +101,6 @@ static void pci4xx_cfgaddr_writel(void *opaque, target_phys_addr_t addr, { PPC4xxPCIState *ppc4xx_pci = opaque; -#ifdef TARGET_WORDS_BIGENDIAN - value = bswap32(value); -#endif - ppc4xx_pci->pci_state.config_reg = value & ~0x3; } @@ -120,10 +115,6 @@ static void ppc4xx_pci_reg_write4(void *opaque, target_phys_addr_t offset, { struct PPC4xxPCIState *pci = opaque; -#ifdef TARGET_WORDS_BIGENDIAN - value = bswap32(value); -#endif - /* We ignore all target attempts at PCI configuration, effectively * assuming a bidirectional 1:1 mapping of PLB and PCI space. */ @@ -251,10 +242,6 @@ static uint32_t ppc4xx_pci_reg_read4(void *opaque, target_phys_addr_t offset) value = 0; } -#ifdef TARGET_WORDS_BIGENDIAN - value = bswap32(value); -#endif - return value; } @@ -373,7 +360,7 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4], /* CFGADDR */ index = cpu_register_io_memory(pci4xx_cfgaddr_read, pci4xx_cfgaddr_write, controller, - DEVICE_NATIVE_ENDIAN); + DEVICE_LITTLE_ENDIAN); if (index < 0) goto free; cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index); @@ -386,7 +373,7 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4], /* Internal registers */ index = cpu_register_io_memory(pci_reg_read, pci_reg_write, controller, - DEVICE_NATIVE_ENDIAN); + DEVICE_LITTLE_ENDIAN); if (index < 0) goto free; cpu_register_physical_memory(registers, PCI_REG_SIZE, index); -- 1.6.0.2