From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=57038 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PPeQJ-0002R2-6i for qemu-devel@nongnu.org; Mon, 06 Dec 2010 12:00:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PPeQE-000645-EQ for qemu-devel@nongnu.org; Mon, 06 Dec 2010 12:00:23 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:34389) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PPeQE-00063W-2Y for qemu-devel@nongnu.org; Mon, 06 Dec 2010 12:00:18 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.69) (envelope-from ) id 1PPeQ7-0007mJ-UG for qemu-devel@nongnu.org; Mon, 06 Dec 2010 17:00:11 +0000 From: Peter Maydell Date: Mon, 6 Dec 2010 17:00:08 +0000 Message-Id: <1291654811-29863-8-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1291654811-29863-1-git-send-email-peter.maydell@linaro.org> References: <1291654811-29863-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 07/10] ARM: Return correct result for single<->double conversion of NaN List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org The ARM ARM defines that if the input to a single<->double conversion is a NaN then the output is always forced to be a quiet NaN by setting the most significant bit of the fraction part. Signed-off-by: Peter Maydell --- target-arm/helper.c | 12 ++++++++++-- 1 files changed, 10 insertions(+), 2 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 6d2a8f2..4bd1cd4 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2528,12 +2528,20 @@ float32 VFP_HELPER(tosiz, d)(float64 x, CPUState *env) /* floating point conversion */ float64 VFP_HELPER(fcvtd, s)(float32 x, CPUState *env) { - return float32_to_float64(x, &env->vfp.fp_status); + float64 r = float32_to_float64(x, &env->vfp.fp_status); + /* ARM requires that S<->D conversion of any kind of NaN generates + * a quiet NaN by forcing the most significant frac bit to 1. + */ + return float64_maybe_silence_nan(r); } float32 VFP_HELPER(fcvts, d)(float64 x, CPUState *env) { - return float64_to_float32(x, &env->vfp.fp_status); + float32 r = float64_to_float32(x, &env->vfp.fp_status); + /* ARM requires that S<->D conversion of any kind of NaN generates + * a quiet NaN by forcing the most significant frac bit to 1. + */ + return float32_maybe_silence_nan(r); } /* VFP3 fixed point conversion. */ -- 1.6.3.3