From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=52521 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PPzhq-0001AY-Gq for qemu-devel@nongnu.org; Tue, 07 Dec 2010 10:44:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PPzhp-0006bt-Al for qemu-devel@nongnu.org; Tue, 07 Dec 2010 10:43:54 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:13451) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PPzho-0006Zf-Ud for qemu-devel@nongnu.org; Tue, 07 Dec 2010 10:43:53 -0500 From: Peter Maydell Date: Tue, 7 Dec 2010 15:43:41 +0000 Message-Id: <1291736623-3695-13-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1291736623-3695-1-git-send-email-peter.maydell@linaro.org> References: <1291736623-3695-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 12/14] ARM: Ignore top 16 bits when doing VCVT from 16 bit fixed point List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori , qemu-devel@nongnu.org VCVT of 16 bit fixed point to float should ignore the top 16 bits of the source register. Cast to int16_t and friends rather than int16 -- the former is guaranteed exactly 16 bits wide where the latter is merely at least 16 bits wide (and so is usually 32 bits). Signed-off-by: Peter Maydell Reviewed-by: Nathan Froyd --- target-arm/helper.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 4bd1cd4..2925782 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2549,7 +2549,7 @@ float32 VFP_HELPER(fcvts, d)(float64 x, CPUState *env) ftype VFP_HELPER(name##to, p)(ftype x, uint32_t shift, CPUState *env) \ { \ ftype tmp; \ - tmp = sign##int32_to_##ftype ((itype)vfp_##p##toi(x), \ + tmp = sign##int32_to_##ftype ((itype##_t)vfp_##p##toi(x), \ &env->vfp.fp_status); \ return ftype##_scalbn(tmp, -(int)shift, &env->vfp.fp_status); \ } \ -- 1.6.3.3