From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=52523 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PPzhq-0001AZ-IQ for qemu-devel@nongnu.org; Tue, 07 Dec 2010 10:43:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PPzho-0006bZ-N1 for qemu-devel@nongnu.org; Tue, 07 Dec 2010 10:43:54 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:13457) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PPzho-0006bD-FW for qemu-devel@nongnu.org; Tue, 07 Dec 2010 10:43:52 -0500 From: Peter Maydell Date: Tue, 7 Dec 2010 15:43:34 +0000 Message-Id: <1291736623-3695-6-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1291736623-3695-1-git-send-email-peter.maydell@linaro.org> References: <1291736623-3695-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 05/14] ARM: Fix decoding of VFP forms of VCVT between float and int/fixed List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori , qemu-devel@nongnu.org Correct the decoding of source and destination registers for the VFP forms of the VCVT instructions which convert between floating point and integer or fixed-point. Signed-off-by: Peter Maydell Reviewed-by: Nathan Froyd --- target-arm/translate.c | 19 ++++++++++++------- 1 files changed, 12 insertions(+), 7 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 7ee5375..69a424a 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -2870,16 +2870,18 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn) VFP_DREG_N(rn, insn); } - if (op == 15 && (rn == 15 || rn > 17)) { + if (op == 15 && (rn == 15 || ((rn & 0x1c) == 0x18))) { /* Integer or single precision destination. */ rd = VFP_SREG_D(insn); } else { VFP_DREG_D(rd, insn); } - - if (op == 15 && (rn == 16 || rn == 17)) { - /* Integer source. */ - rm = ((insn << 1) & 0x1e) | ((insn >> 5) & 1); + if (op == 15 && + (((rn & 0x1c) == 0x10) || ((rn & 0x14) == 0x14))) { + /* VCVT from int is always from S reg regardless of dp bit. + * VCVT with immediate frac_bits has same format as SREG_M + */ + rm = VFP_SREG_M(insn); } else { VFP_DREG_M(rm, insn); } @@ -2891,6 +2893,9 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn) } else { rd = VFP_SREG_D(insn); } + /* NB that we implicitly rely on the encoding for the frac_bits + * in VCVT of fixed to float being the same as that of an SREG_M + */ rm = VFP_SREG_M(insn); } @@ -3179,8 +3184,8 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn) /* Write back the result. */ if (op == 15 && (rn >= 8 && rn <= 11)) ; /* Comparison, do nothing. */ - else if (op == 15 && rn > 17) - /* Integer result. */ + else if (op == 15 && dp && ((rn & 0x1c) == 0x18)) + /* VCVT double to int: always integer result. */ gen_mov_vreg_F0(0, rd); else if (op == 15 && rn == 15) /* conversion */ -- 1.6.3.3