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From: Aurelien Jarno <aurelien@aurel32.net>
To: qemu-devel@nongnu.org
Cc: Aurelien Jarno <aurelien@aurel32.net>
Subject: [Qemu-devel] [PATCH] TCG: Improve tb_phys_hash_func()
Date: Wed, 29 Dec 2010 22:27:24 +0100	[thread overview]
Message-ID: <1293658044-10244-1-git-send-email-aurelien@aurel32.net> (raw)

Most of emulated CPU have instructions aligned on 16 or 32 bits, while
on others GCC tries to align the target jump location. This means that
1/2 or 3/4 of tb_phys_hash entries are never used.

Update the hash function tb_phys_hash_func() to ignore the two lowest
bits of the address. This brings a 6% speed-up when booting a MIPS
image.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 exec-all.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/exec-all.h b/exec-all.h
index 6821b17..a4b75bd 100644
--- a/exec-all.h
+++ b/exec-all.h
@@ -177,7 +177,7 @@ static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
 
 static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc)
 {
-    return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
+    return (pc >> 2) & (CODE_GEN_PHYS_HASH_SIZE - 1);
 }
 
 TranslationBlock *tb_alloc(target_ulong pc);
-- 
1.7.2.3

             reply	other threads:[~2010-12-29 21:27 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-12-29 21:27 Aurelien Jarno [this message]
2010-12-30 17:55 ` [Qemu-devel] [PATCH] TCG: Improve tb_phys_hash_func() Blue Swirl
2010-12-31 19:46   ` Aurelien Jarno
2010-12-31 19:55     ` Aurelien Jarno

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