From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=34904 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PY3YO-0008QK-HP for qemu-devel@nongnu.org; Wed, 29 Dec 2010 16:27:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PY3YN-0006Ks-Bm for qemu-devel@nongnu.org; Wed, 29 Dec 2010 16:27:28 -0500 Received: from hall.aurel32.net ([88.191.126.93]:60173) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PY3YN-0006Km-2u for qemu-devel@nongnu.org; Wed, 29 Dec 2010 16:27:27 -0500 From: Aurelien Jarno Date: Wed, 29 Dec 2010 22:27:24 +0100 Message-Id: <1293658044-10244-1-git-send-email-aurelien@aurel32.net> Subject: [Qemu-devel] [PATCH] TCG: Improve tb_phys_hash_func() List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Aurelien Jarno Most of emulated CPU have instructions aligned on 16 or 32 bits, while on others GCC tries to align the target jump location. This means that 1/2 or 3/4 of tb_phys_hash entries are never used. Update the hash function tb_phys_hash_func() to ignore the two lowest bits of the address. This brings a 6% speed-up when booting a MIPS image. Signed-off-by: Aurelien Jarno --- exec-all.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/exec-all.h b/exec-all.h index 6821b17..a4b75bd 100644 --- a/exec-all.h +++ b/exec-all.h @@ -177,7 +177,7 @@ static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc) static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc) { - return pc & (CODE_GEN_PHYS_HASH_SIZE - 1); + return (pc >> 2) & (CODE_GEN_PHYS_HASH_SIZE - 1); } TranslationBlock *tb_alloc(target_ulong pc); -- 1.7.2.3