From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=54831 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PYlzy-0004mg-Ki for qemu-devel@nongnu.org; Fri, 31 Dec 2010 15:54:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PYlzw-0003bB-Jd for qemu-devel@nongnu.org; Fri, 31 Dec 2010 15:54:54 -0500 Received: from hall.aurel32.net ([88.191.126.93]:48519) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PYlzw-0003ai-FB for qemu-devel@nongnu.org; Fri, 31 Dec 2010 15:54:52 -0500 From: Aurelien Jarno Date: Fri, 31 Dec 2010 21:54:40 +0100 Message-Id: <1293828880-25429-1-git-send-email-aurelien@aurel32.net> Subject: [Qemu-devel] [PATCH v2] target-arm: fix UMAAL instruction List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Aurelien Jarno UMAAL should use unsigned multiply instead of signed. This patch fixes this issue by handling UMAAL separately from UMULL/UMLAL/SMULL/SMLAL as these instructions are different enough. It also explicitly list instructions in case and catch nonexistent instruction as illegal. Also fixes a few style issues. This fixes the issues reported in https://bugs.launchpad.net/qemu/+bug/696015 Cc: Peter Maydell Signed-off-by: Aurelien Jarno --- target-arm/translate.c | 32 ++++++++++++++++++++++---------- 1 files changed, 22 insertions(+), 10 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 8d494ec..2598268 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -6637,26 +6637,38 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) gen_logic_CC(tmp); store_reg(s, rd, tmp); break; - default: - /* 64 bit mul */ + case 4: + /* 64 bit mul double accumulate (UMAAL) */ + ARCH(6); tmp = load_reg(s, rs); tmp2 = load_reg(s, rm); - if (insn & (1 << 22)) + tmp64 = gen_mulu_i64_i32(tmp, tmp2); + gen_addq_lo(s, tmp64, rn); + gen_addq_lo(s, tmp64, rd); + gen_storeq_reg(s, rn, rd, tmp64); + tcg_temp_free_i64(tmp64); + break; + case 8: case 9: case 10: case 11: + case 12: case 13: case 14: case 15: + /* 64 bit mul: UMULL, UMLAL, SMULL, SMLAL. */ + tmp = load_reg(s, rs); + tmp2 = load_reg(s, rm); + if (insn & (1 << 22)) { tmp64 = gen_muls_i64_i32(tmp, tmp2); - else + } else { tmp64 = gen_mulu_i64_i32(tmp, tmp2); - if (insn & (1 << 21)) /* mult accumulate */ + } + if (insn & (1 << 21)) { /* mult accumulate */ gen_addq(s, tmp64, rn, rd); - if (!(insn & (1 << 23))) { /* double accumulate */ - ARCH(6); - gen_addq_lo(s, tmp64, rn); - gen_addq_lo(s, tmp64, rd); } - if (insn & (1 << 20)) + if (insn & (1 << 20)) { gen_logicq_cc(tmp64); + } gen_storeq_reg(s, rn, rd, tmp64); tcg_temp_free_i64(tmp64); break; + default: + goto illegal_op; } } else { rn = (insn >> 16) & 0xf; -- 1.7.2.3