[Qemu-devel] (no subject)

[Qemu-devel] (no subject)

[Aurelien Jarno]

This patch series start by a cleanup to remove dead HPPA code and fix a
few inconsistencies. The following patch implement implement correct
NaN propagation rules for MIPS and PowerPC, following commit 3
54f211b1a49a7387929e22d6e63849fcba48f8a.

Changes from v1:
- Add "softfloat: use bits32 instead of uint32" (missing in previous
  series)
- Add "softfloat: rename *IsNaN variables to *IsQuietNaN" as suggested
  by Peter Maydell.
- Update "softfloat: fix float{32,64}_maybe_silence_nan() for MIPS" and
  "softfloat: add float{x80,128}_maybe_silence_nan()" to issue a compile
  error on SNAN_BIT_IS_ONE targets other than MIPS.
- Update "softfloat: use float{32,64,x80,128}_maybe_silence_nan()" to 
  correctly compute aIsLargerSignificand.

[Qemu-devel] [PATCH v2 1/8] softfloat: remove HPPA specific code

[Aurelien Jarno]

We don't have any HPPA target, so let's remove HPPA specific code. It
can be re-added when someone adds an HPPA target.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
 fpu/softfloat-specialize.h |    6 +-----
 1 files changed, 1 insertions(+), 5 deletions(-)

diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index f43f2d0a..5da3a85 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -30,7 +30,7 @@ these four paragraphs for those parts of this code that are retained.
 
 =============================================================================*/
 
-#if defined(TARGET_MIPS) || defined(TARGET_HPPA)
+#if defined(TARGET_MIPS)
 #define SNAN_BIT_IS_ONE		1
 #else
 #define SNAN_BIT_IS_ONE		0
@@ -63,8 +63,6 @@ typedef struct {
 #define float32_default_nan make_float32(0x7FFFFFFF)
 #elif defined(TARGET_POWERPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA)
 #define float32_default_nan make_float32(0x7FC00000)
-#elif defined(TARGET_HPPA)
-#define float32_default_nan make_float32(0x7FA00000)
 #elif SNAN_BIT_IS_ONE
 #define float32_default_nan make_float32(0x7FBFFFFF)
 #else
@@ -275,8 +273,6 @@ static float32 propagateFloat32NaN( float32 a, float32 b STATUS_PARAM)
 #define float64_default_nan make_float64(LIT64( 0x7FFFFFFFFFFFFFFF ))
 #elif defined(TARGET_POWERPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA)
 #define float64_default_nan make_float64(LIT64( 0x7FF8000000000000 ))
-#elif defined(TARGET_HPPA)
-#define float64_default_nan make_float64(LIT64( 0x7FF4000000000000 ))
 #elif SNAN_BIT_IS_ONE
 #define float64_default_nan make_float64(LIT64( 0x7FF7FFFFFFFFFFFF ))
 #else
-- 
1.7.2.3

[Qemu-devel] [PATCH v2 2/8] softfloat: use bits32 instead of uint32

[Aurelien Jarno]

Use bits32 instead of uint32 when manipulating floating point values
directly for consistency reasons.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 fpu/softfloat-native.c     |    4 ++--
 fpu/softfloat-specialize.h |    6 +++---
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/fpu/softfloat-native.c b/fpu/softfloat-native.c
index 008bb53..5c737b7 100644
--- a/fpu/softfloat-native.c
+++ b/fpu/softfloat-native.c
@@ -248,7 +248,7 @@ int float32_compare_quiet( float32 a, float32 b STATUS_PARAM )
 int float32_is_signaling_nan( float32 a1)
 {
     float32u u;
-    uint32_t a;
+    bits32 a;
     u.f = a1;
     a = u.i;
     return ( ( ( a>>22 ) & 0x1FF ) == 0x1FE ) && ( a & 0x003FFFFF );
@@ -257,7 +257,7 @@ int float32_is_signaling_nan( float32 a1)
 int float32_is_quiet_nan( float32 a1 )
 {
     float32u u;
-    uint64_t a;
+    bits32 a;
     u.f = a1;
     a = u.i;
     return ( 0xFF800000 < ( a<<1 ) );
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 5da3a85..f23bd6a 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -76,7 +76,7 @@ typedef struct {
 
 int float32_is_quiet_nan( float32 a_ )
 {
-    uint32_t a = float32_val(a_);
+    bits32 a = float32_val(a_);
 #if SNAN_BIT_IS_ONE
     return ( ( ( a>>22 ) & 0x1FF ) == 0x1FE ) && ( a & 0x003FFFFF );
 #else
@@ -91,7 +91,7 @@ int float32_is_quiet_nan( float32 a_ )
 
 int float32_is_signaling_nan( float32 a_ )
 {
-    uint32_t a = float32_val(a_);
+    bits32 a = float32_val(a_);
 #if SNAN_BIT_IS_ONE
     return ( 0xFF800000 <= (bits32) ( a<<1 ) );
 #else
@@ -107,7 +107,7 @@ int float32_is_signaling_nan( float32 a_ )
 float32 float32_maybe_silence_nan( float32 a_ )
 {
     if (float32_is_signaling_nan(a_)) {
-        uint32_t a = float32_val(a_);
+        bits32 a = float32_val(a_);
 #if SNAN_BIT_IS_ONE
         a &= ~(1 << 22);
 #else
-- 
1.7.2.3

Re: [Qemu-devel] [PATCH v2 2/8] softfloat: use bits32 instead of uint32

[Peter Maydell]

On 4 January 2011 15:15, Aurelien Jarno <aurelien@aurel32.net> wrote:
> Use bits32 instead of uint32 when manipulating floating point values
> directly for consistency reasons.

I'm not convinced this patch is particularly worthwhile, especially since
Andreas is working on a patchset which will convert all the bits32
uses back into uint32_t anyway, which is the direction to go if we
want to make the fpu/ code consistent about its type usage.

If you do want to do this, the commit message should be "uint32_t"
not "uint32" (which is a different type!)

>  int float32_is_quiet_nan( float32 a1 )
>  {
>     float32u u;
> -    uint64_t a;
> +    bits32 a;
>     u.f = a1;
>     a = u.i;
>     return ( 0xFF800000 < ( a<<1 ) );

This change is actually changing the type: shouldn't it be bits64 ?

It seems a bit inconsistent to change softfloat-native.c:float32_is_quiet_nan()
but not softfloat-native.c:float64_is_quiet_nan() (which uses uint64_t).

Personally I'd just drop this patch.

-- PMM

Re: [Qemu-devel] [PATCH v2 2/8] softfloat: use bits32 instead of uint32

[Aurelien Jarno]

On Tue, Jan 04, 2011 at 03:51:37PM +0000, Peter Maydell wrote:
> On 4 January 2011 15:15, Aurelien Jarno <aurelien@aurel32.net> wrote:
> > Use bits32 instead of uint32 when manipulating floating point values
> > directly for consistency reasons.
> 
> I'm not convinced this patch is particularly worthwhile, especially since
> Andreas is working on a patchset which will convert all the bits32
> uses back into uint32_t anyway, which is the direction to go if we
> want to make the fpu/ code consistent about its type usage.

I don't know in which direction we should go (bits32 or uint32_t), but
we should go for more consistency. When everything is consistent, it's
just a regex to go switch the type.

> If you do want to do this, the commit message should be "uint32_t"
> not "uint32" (which is a different type!)

Correct.

> >  int float32_is_quiet_nan( float32 a1 )
> >  {
> >     float32u u;
> > -    uint64_t a;
> > +    bits32 a;
> >     u.f = a1;
> >     a = u.i;
> >     return ( 0xFF800000 < ( a<<1 ) );
> 
> This change is actually changing the type: shouldn't it be bits64 ?

Yes, I should have mentioned it in the changelog. For me this looks like
a typo, as we are manipulating 32 bits values. Look at
float32_is_signaling_nan().

> It seems a bit inconsistent to change softfloat-native.c:float32_is_quiet_nan()
> but not softfloat-native.c:float64_is_quiet_nan() (which uses uint64_t).

I guess you meant softfloat-native.c:float32_is_quiet_nan(). It looks
like I missed this one, and that it should be changed too.

> Personally I'd just drop this patch.

I'll drop it for now and wait to see what Andreas offers.

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

Re: [Qemu-devel] [PATCH v2 2/8] softfloat: use bits32 instead of uint32

[Peter Maydell]

On 4 January 2011 16:11, Aurelien Jarno <aurelien@aurel32.net> wrote:
> On Tue, Jan 04, 2011 at 03:51:37PM +0000, Peter Maydell wrote:
>> >  int float32_is_quiet_nan( float32 a1 )
>> >  {
>> >     float32u u;
>> > -    uint64_t a;
>> > +    bits32 a;
>> >     u.f = a1;
>> >     a = u.i;
>> >     return ( 0xFF800000 < ( a<<1 ) );
>>
>> This change is actually changing the type: shouldn't it be bits64 ?
>
> Yes, I should have mentioned it in the changelog. For me this looks like
> a typo, as we are manipulating 32 bits values. Look at
> float32_is_signaling_nan().

Well, it does affect whether that left-shift of a loses the sign bit
or not. However having thought about it it doesn't make any
difference to the result of the comparison, so bits32 would be OK.

On the other hand, this should be a "<=" compare, not "<", I think.
0x7FC00000 is a valid QNaN but this function will return false for
it. Contrast the softfloat-specialize.h float32_is_quiet_nan()
implementation for !SNAN_BIT_IS_ONE, which does use <=.

(On the third hand if you're using softfloat-native then you
probably didn't care about the niceties of NaN usage :-))

-- PMM

Re: [Qemu-devel] [PATCH v2 2/8] softfloat: use bits32 instead of uint32

[Andreas Färber]

Am 04.01.2011 um 17:11 schrieb Aurelien Jarno:

> On Tue, Jan 04, 2011 at 03:51:37PM +0000, Peter Maydell wrote:
>> On 4 January 2011 15:15, Aurelien Jarno <aurelien@aurel32.net> wrote:
>>> Use bits32 instead of uint32 when manipulating floating point values
>>> directly for consistency reasons.
>>
>> I'm not convinced this patch is particularly worthwhile, especially  
>> since
>> Andreas is working on a patchset which will convert all the bits32
>> uses back into uint32_t anyway, which is the direction to go if we
>> want to make the fpu/ code consistent about its type usage.
>
> I don't know in which direction we should go (bits32 or uint32_t), but
> we should go for more consistency. When everything is consistent, it's
> just a regex to go switch the type.

Please don't introduce new uses of bits*. There's simply no reason to  
have such types in a C99 project.

Unfortunately the new year started with hardware failure for me, so I  
haven't found the time to continue work on the series yet. I'll send a  
rebased v4 shortly, patch 5/7 v3 was broken by a change to softfloat- 
specialize.h.

Andreas

[Qemu-devel] [PATCH v2 3/8] softfloat: rename *IsNaN variables to *IsQuietNaN

[Aurelien Jarno]

Similarly to what has been done in commit
185698715dfb18c82ad2a5dbc169908602d43e81 rename the misnamed *IsNaN
variables into *IsQuietNaN.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 fpu/softfloat-specialize.h |   36 ++++++++++++++++++++----------------
 1 files changed, 20 insertions(+), 16 deletions(-)

diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index f23bd6a..0003cbe 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -227,15 +227,16 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
 
 static float32 propagateFloat32NaN( float32 a, float32 b STATUS_PARAM)
 {
-    flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN, aIsLargerSignificand;
+    flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN;
+    flag aIsLargerSignificand;
     bits32 av, bv, res;
 
     if ( STATUS(default_nan_mode) )
         return float32_default_nan;
 
-    aIsNaN = float32_is_quiet_nan( a );
+    aIsQuietNaN = float32_is_quiet_nan( a );
     aIsSignalingNaN = float32_is_signaling_nan( a );
-    bIsNaN = float32_is_quiet_nan( b );
+    bIsQuietNaN = float32_is_quiet_nan( b );
     bIsSignalingNaN = float32_is_signaling_nan( b );
     av = float32_val(a);
     bv = float32_val(b);
@@ -256,7 +257,7 @@ static float32 propagateFloat32NaN( float32 a, float32 b STATUS_PARAM)
         aIsLargerSignificand = (av < bv) ? 1 : 0;
     }
 
-    if (pickNaN(aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN,
+    if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
                 aIsLargerSignificand)) {
         res = bv;
     } else {
@@ -375,15 +376,16 @@ static float64 commonNaNToFloat64( commonNaNT a )
 
 static float64 propagateFloat64NaN( float64 a, float64 b STATUS_PARAM)
 {
-    flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN, aIsLargerSignificand;
+    flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN;
+    flag aIsLargerSignificand;
     bits64 av, bv, res;
 
     if ( STATUS(default_nan_mode) )
         return float64_default_nan;
 
-    aIsNaN = float64_is_quiet_nan( a );
+    aIsQuietNaN = float64_is_quiet_nan( a );
     aIsSignalingNaN = float64_is_signaling_nan( a );
-    bIsNaN = float64_is_quiet_nan( b );
+    bIsQuietNaN = float64_is_quiet_nan( b );
     bIsSignalingNaN = float64_is_signaling_nan( b );
     av = float64_val(a);
     bv = float64_val(b);
@@ -404,7 +406,7 @@ static float64 propagateFloat64NaN( float64 a, float64 b STATUS_PARAM)
         aIsLargerSignificand = (av < bv) ? 1 : 0;
     }
 
-    if (pickNaN(aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN,
+    if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
                 aIsLargerSignificand)) {
         res = bv;
     } else {
@@ -511,7 +513,8 @@ static floatx80 commonNaNToFloatx80( commonNaNT a )
 
 static floatx80 propagateFloatx80NaN( floatx80 a, floatx80 b STATUS_PARAM)
 {
-    flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN, aIsLargerSignificand;
+    flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN;
+    flag aIsLargerSignificand;
 
     if ( STATUS(default_nan_mode) ) {
         a.low = floatx80_default_nan_low;
@@ -519,9 +522,9 @@ static floatx80 propagateFloatx80NaN( floatx80 a, floatx80 b STATUS_PARAM)
         return a;
     }
 
-    aIsNaN = floatx80_is_quiet_nan( a );
+    aIsQuietNaN = floatx80_is_quiet_nan( a );
     aIsSignalingNaN = floatx80_is_signaling_nan( a );
-    bIsNaN = floatx80_is_quiet_nan( b );
+    bIsQuietNaN = floatx80_is_quiet_nan( b );
     bIsSignalingNaN = floatx80_is_signaling_nan( b );
 #if SNAN_BIT_IS_ONE
     a.low &= ~LIT64( 0xC000000000000000 );
@@ -540,7 +543,7 @@ static floatx80 propagateFloatx80NaN( floatx80 a, floatx80 b STATUS_PARAM)
         aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
     }
 
-    if (pickNaN(aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN,
+    if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
                 aIsLargerSignificand)) {
         return b;
     } else {
@@ -638,7 +641,8 @@ static float128 commonNaNToFloat128( commonNaNT a )
 
 static float128 propagateFloat128NaN( float128 a, float128 b STATUS_PARAM)
 {
-    flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN, aIsLargerSignificand;
+    flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN;
+    flag aIsLargerSignificand;
 
     if ( STATUS(default_nan_mode) ) {
         a.low = float128_default_nan_low;
@@ -646,9 +650,9 @@ static float128 propagateFloat128NaN( float128 a, float128 b STATUS_PARAM)
         return a;
     }
 
-    aIsNaN = float128_is_quiet_nan( a );
+    aIsQuietNaN = float128_is_quiet_nan( a );
     aIsSignalingNaN = float128_is_signaling_nan( a );
-    bIsNaN = float128_is_quiet_nan( b );
+    bIsQuietNaN = float128_is_quiet_nan( b );
     bIsSignalingNaN = float128_is_signaling_nan( b );
 #if SNAN_BIT_IS_ONE
     a.high &= ~LIT64( 0x0000800000000000 );
@@ -667,7 +671,7 @@ static float128 propagateFloat128NaN( float128 a, float128 b STATUS_PARAM)
         aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
     }
 
-    if (pickNaN(aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN,
+    if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
                 aIsLargerSignificand)) {
         return b;
     } else {
-- 
1.7.2.3

Re: [Qemu-devel] [PATCH v2 3/8] softfloat: rename *IsNaN variables to *IsQuietNaN

[Peter Maydell]

On 4 January 2011 15:15, Aurelien Jarno <aurelien@aurel32.net> wrote:
> Similarly to what has been done in commit
> 185698715dfb18c82ad2a5dbc169908602d43e81 rename the misnamed *IsNaN
> variables into *IsQuietNaN.
>
> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

-- PMM

[Qemu-devel] [PATCH v2 4/8] softfloat: fix float{32, 64}_maybe_silence_nan() for MIPS

[Aurelien Jarno]

On targets that define sNaN with the sNaN bit as one, simply clearing
this bit may correspond to an infinite value.

Convert it to a default NaN if SNAN_BIT_IS_ONE, as it corresponds to
the MIPS implementation, the only emulated CPU with SNAN_BIT_IS_ONE.
When other CPU of this type are added, this might be updated to include
more cases.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 fpu/softfloat-specialize.h |   20 ++++++++++++++------
 1 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 0003cbe..ac26214 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -107,13 +107,17 @@ int float32_is_signaling_nan( float32 a_ )
 float32 float32_maybe_silence_nan( float32 a_ )
 {
     if (float32_is_signaling_nan(a_)) {
-        bits32 a = float32_val(a_);
 #if SNAN_BIT_IS_ONE
-        a &= ~(1 << 22);
+#  if defined(TARGET_MIPS)
+        return float32_default_nan;
+#  else
+#    error Rules for silencing a signaling NaN are target-specific
+#  endif
 #else
+        bits32 a = float32_val(a_);
         a |= (1 << 22);
-#endif
         return make_float32(a);
+#endif
     }
     return a_;
 }
@@ -322,13 +326,17 @@ int float64_is_signaling_nan( float64 a_ )
 float64 float64_maybe_silence_nan( float64 a_ )
 {
     if (float64_is_signaling_nan(a_)) {
-        bits64 a = float64_val(a_);
 #if SNAN_BIT_IS_ONE
-        a &= ~LIT64( 0x0008000000000000 );
+#  if defined(TARGET_MIPS)
+        return float64_default_nan;
+#  else
+#    error Rules for silencing a signaling NaN are target-specific
+#  endif
 #else
+        bits64 a = float64_val(a_);
         a |= LIT64( 0x0008000000000000 );
-#endif
         return make_float64(a);
+#endif
     }
     return a_;
 }
-- 
1.7.2.3

[Qemu-devel] [PATCH v2 5/8] softfloat: add float{x80, 128}_maybe_silence_nan()

[Aurelien Jarno]

Add float{x80,128}_maybe_silence_nan() functions, they will be need by
propagateFloat{x80,128}NaN().

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
 fpu/softfloat-specialize.h |   46 ++++++++++++++++++++++++++++++++++++++++++++
 fpu/softfloat.h            |    2 +
 2 files changed, 48 insertions(+), 0 deletions(-)

diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index ac26214..f5374cf 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -480,6 +480,29 @@ int floatx80_is_signaling_nan( floatx80 a )
 }
 
 /*----------------------------------------------------------------------------
+| Returns a quiet NaN if the extended double-precision floating point value
+| `a' is a signaling NaN; otherwise returns `a'.
+*----------------------------------------------------------------------------*/
+
+floatx80 floatx80_maybe_silence_nan( floatx80 a )
+{
+    if (floatx80_is_signaling_nan(a)) {
+#if SNAN_BIT_IS_ONE
+#  if defined(TARGET_MIPS)
+        a.low = floatx80_default_nan_low;
+        a.high = floatx80_default_nan_high;
+#  else
+#    error Rules for silencing a signaling NaN are target-specific
+#  endif
+#else
+        a.low |= LIT64( 0xC000000000000000 );
+        return a;
+#endif
+    }
+    return a;
+}
+
+/*----------------------------------------------------------------------------
 | Returns the result of converting the extended double-precision floating-
 | point NaN `a' to the canonical NaN format.  If `a' is a signaling NaN, the
 | invalid exception is raised.
@@ -612,6 +635,29 @@ int float128_is_signaling_nan( float128 a )
 }
 
 /*----------------------------------------------------------------------------
+| Returns a quiet NaN if the quadruple-precision floating point value `a' is
+| a signaling NaN; otherwise returns `a'.
+*----------------------------------------------------------------------------*/
+
+float128 float128_maybe_silence_nan( float128 a )
+{
+    if (float128_is_signaling_nan(a)) {
+#if SNAN_BIT_IS_ONE
+#  if defined(TARGET_MIPS)
+        a.low = float128_default_nan_low;
+        a.high = float128_default_nan_high;
+#  else
+#    error Rules for silencing a signaling NaN are target-specific
+#  endif
+#else
+        a.high |= LIT64( 0x0000800000000000 );
+        return a;
+#endif
+    }
+    return a;
+}
+
+/*----------------------------------------------------------------------------
 | Returns the result of converting the quadruple-precision floating-point NaN
 | `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid
 | exception is raised.
diff --git a/fpu/softfloat.h b/fpu/softfloat.h
index 1f37877..f2104c6 100644
--- a/fpu/softfloat.h
+++ b/fpu/softfloat.h
@@ -439,6 +439,7 @@ int floatx80_le_quiet( floatx80, floatx80 STATUS_PARAM );
 int floatx80_lt_quiet( floatx80, floatx80 STATUS_PARAM );
 int floatx80_is_quiet_nan( floatx80 );
 int floatx80_is_signaling_nan( floatx80 );
+floatx80 floatx80_maybe_silence_nan( floatx80 );
 floatx80 floatx80_scalbn( floatx80, int STATUS_PARAM );
 
 INLINE floatx80 floatx80_abs(floatx80 a)
@@ -505,6 +506,7 @@ int float128_compare( float128, float128 STATUS_PARAM );
 int float128_compare_quiet( float128, float128 STATUS_PARAM );
 int float128_is_quiet_nan( float128 );
 int float128_is_signaling_nan( float128 );
+float128 float128_maybe_silence_nan( float128 );
 float128 float128_scalbn( float128, int STATUS_PARAM );
 
 INLINE float128 float128_abs(float128 a)
-- 
1.7.2.3

[Qemu-devel] [PATCH v2 6/8] softfloat: use float{32, 64, x80, 128}_maybe_silence_nan()

[Aurelien Jarno]

Use float{32,64,x80,128}_maybe_silence_nan() instead of toggling the
sNaN bit manually. This allow per target implementation of sNaN to qNaN
conversion.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 fpu/softfloat-specialize.h |   59 ++++++++++++--------------------------------
 1 files changed, 16 insertions(+), 43 deletions(-)

diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index f5374cf..060e3fd 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -161,7 +161,8 @@ static float32 commonNaNToFloat32( commonNaNT a )
 | The routine is passed various bits of information about the
 | two NaNs and should return 0 to select NaN a and 1 for NaN b.
 | Note that signalling NaNs are always squashed to quiet NaNs
-| by the caller, by flipping the SNaN bit before returning them.
+| by the caller, by calling floatXX_maybe_silence_nan() before
+| returning them.
 |
 | aIsLargerSignificand is only valid if both a and b are NaNs
 | of some kind, and is true if a has the larger significand,
@@ -233,7 +234,7 @@ static float32 propagateFloat32NaN( float32 a, float32 b STATUS_PARAM)
 {
     flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN;
     flag aIsLargerSignificand;
-    bits32 av, bv, res;
+    bits32 av, bv;
 
     if ( STATUS(default_nan_mode) )
         return float32_default_nan;
@@ -244,13 +245,7 @@ static float32 propagateFloat32NaN( float32 a, float32 b STATUS_PARAM)
     bIsSignalingNaN = float32_is_signaling_nan( b );
     av = float32_val(a);
     bv = float32_val(b);
-#if SNAN_BIT_IS_ONE
-    av &= ~0x00400000;
-    bv &= ~0x00400000;
-#else
-    av |= 0x00400000;
-    bv |= 0x00400000;
-#endif
+
     if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid STATUS_VAR);
 
     if ((bits32)(av<<1) < (bits32)(bv<<1)) {
@@ -263,12 +258,10 @@ static float32 propagateFloat32NaN( float32 a, float32 b STATUS_PARAM)
 
     if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
                 aIsLargerSignificand)) {
-        res = bv;
+        return float32_maybe_silence_nan(b);
     } else {
-        res = av;
+        return float32_maybe_silence_nan(a);
     }
-
-    return make_float32(res);
 }
 
 /*----------------------------------------------------------------------------
@@ -386,7 +379,7 @@ static float64 propagateFloat64NaN( float64 a, float64 b STATUS_PARAM)
 {
     flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN;
     flag aIsLargerSignificand;
-    bits64 av, bv, res;
+    bits64 av, bv;
 
     if ( STATUS(default_nan_mode) )
         return float64_default_nan;
@@ -397,13 +390,7 @@ static float64 propagateFloat64NaN( float64 a, float64 b STATUS_PARAM)
     bIsSignalingNaN = float64_is_signaling_nan( b );
     av = float64_val(a);
     bv = float64_val(b);
-#if SNAN_BIT_IS_ONE
-    av &= ~LIT64( 0x0008000000000000 );
-    bv &= ~LIT64( 0x0008000000000000 );
-#else
-    av |= LIT64( 0x0008000000000000 );
-    bv |= LIT64( 0x0008000000000000 );
-#endif
+
     if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid STATUS_VAR);
 
     if ((bits64)(av<<1) < (bits64)(bv<<1)) {
@@ -416,12 +403,10 @@ static float64 propagateFloat64NaN( float64 a, float64 b STATUS_PARAM)
 
     if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
                 aIsLargerSignificand)) {
-        res = bv;
+        return float64_maybe_silence_nan(b);
     } else {
-        res = av;
+        return float64_maybe_silence_nan(a);
     }
-
-    return make_float64(res);
 }
 
 #ifdef FLOATX80
@@ -557,13 +542,7 @@ static floatx80 propagateFloatx80NaN( floatx80 a, floatx80 b STATUS_PARAM)
     aIsSignalingNaN = floatx80_is_signaling_nan( a );
     bIsQuietNaN = floatx80_is_quiet_nan( b );
     bIsSignalingNaN = floatx80_is_signaling_nan( b );
-#if SNAN_BIT_IS_ONE
-    a.low &= ~LIT64( 0xC000000000000000 );
-    b.low &= ~LIT64( 0xC000000000000000 );
-#else
-    a.low |= LIT64( 0xC000000000000000 );
-    b.low |= LIT64( 0xC000000000000000 );
-#endif
+
     if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid STATUS_VAR);
 
     if (a.low < b.low) {
@@ -576,9 +555,9 @@ static floatx80 propagateFloatx80NaN( floatx80 a, floatx80 b STATUS_PARAM)
 
     if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
                 aIsLargerSignificand)) {
-        return b;
+        return floatx80_maybe_silence_nan(b);
     } else {
-        return a;
+        return floatx80_maybe_silence_nan(a);
     }
 }
 
@@ -708,13 +687,7 @@ static float128 propagateFloat128NaN( float128 a, float128 b STATUS_PARAM)
     aIsSignalingNaN = float128_is_signaling_nan( a );
     bIsQuietNaN = float128_is_quiet_nan( b );
     bIsSignalingNaN = float128_is_signaling_nan( b );
-#if SNAN_BIT_IS_ONE
-    a.high &= ~LIT64( 0x0000800000000000 );
-    b.high &= ~LIT64( 0x0000800000000000 );
-#else
-    a.high |= LIT64( 0x0000800000000000 );
-    b.high |= LIT64( 0x0000800000000000 );
-#endif
+
     if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid STATUS_VAR);
 
     if (lt128(a.high<<1, a.low, b.high<<1, b.low)) {
@@ -727,9 +700,9 @@ static float128 propagateFloat128NaN( float128 a, float128 b STATUS_PARAM)
 
     if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
                 aIsLargerSignificand)) {
-        return b;
+        return float128_maybe_silence_nan(b);
     } else {
-        return a;
+        return float128_maybe_silence_nan(a);
     }
 }
 
-- 
1.7.2.3

Re: [Qemu-devel] [PATCH v2 6/8] softfloat: use float{32, 64, x80, 128}_maybe_silence_nan()

[Peter Maydell]

On 4 January 2011 15:15, Aurelien Jarno <aurelien@aurel32.net> wrote:
> Use float{32,64,x80,128}_maybe_silence_nan() instead of toggling the
> sNaN bit manually. This allow per target implementation of sNaN to qNaN
> conversion.
>
> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

-- PMM

[Qemu-devel] [PATCH v2 7/8] target-mips: Implement correct NaN propagation rules

[Aurelien Jarno]

Implement the correct NaN propagation rules for MIPS targets by
providing an appropriate pickNaN function.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 fpu/softfloat-specialize.h |   27 +++++++++++++++++++++++++++
 1 files changed, 27 insertions(+), 0 deletions(-)

diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 060e3fd..1d4eab8 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -192,6 +192,33 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
         return 1;
     }
 }
+#elif defined(TARGET_MIPS)
+static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
+                    flag aIsLargerSignificand)
+{
+    /* According to MIPS specifications, if one of the two operands is
+     * a sNaN, a new qNaN has to be generated. This is done in
+     * floatXX_maybe_silence_nan(). For qNaN inputs the specifications
+     * says: "When possible, this QNaN result is one of the operand QNaN
+     * values." In practice it seems that most implementations choose
+     * the first operand if both operands are qNaN. In short this gives
+     * the following rules:
+     *  1. A if it is signaling
+     *  2. B if it is signaling
+     *  3. A (quiet)
+     *  4. B (quiet)
+     * A signaling NaN is always quietened before returning it.
+     */
+    if (aIsSNaN) {
+        return 0;
+    } else if (bIsSNaN) {
+        return 1;
+    } else if (aIsQNaN) {
+        return 0;
+    } else {
+        return 1;
+    }
+}
 #else
 static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
                     flag aIsLargerSignificand)
-- 
1.7.2.3

[Qemu-devel] [PATCH v2 8/8] target-ppc: Implement correct NaN propagation rules

[Aurelien Jarno]

Implement the correct NaN propagation rules for ARM targets by
providing an appropriate pickNaN function.

Also fix the #ifdef tests for default NaN definition, the correct name
is TARGET_PPC instead of TARGET_POWERPC.

Cc: Alexander Graf <agraf@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 fpu/softfloat-specialize.h |   19 +++++++++++++++++--
 1 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 1d4eab8..8835125 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -61,7 +61,7 @@ typedef struct {
 *----------------------------------------------------------------------------*/
 #if defined(TARGET_SPARC)
 #define float32_default_nan make_float32(0x7FFFFFFF)
-#elif defined(TARGET_POWERPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA)
+#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA)
 #define float32_default_nan make_float32(0x7FC00000)
 #elif SNAN_BIT_IS_ONE
 #define float32_default_nan make_float32(0x7FBFFFFF)
@@ -219,6 +219,21 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
         return 1;
     }
 }
+#elif defined(TARGET_PPC)
+static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
+                   flag aIsLargerSignificand)
+{
+    /* PowerPC propagation rules:
+     *  1. A if it sNaN or qNaN
+     *  2. B if it sNaN or qNaN
+     * A signaling NaN is always quietened before returning it.
+     */
+    if (aIsSNaN || aIsQNaN) {
+        return 0;
+    } else {
+        return 1;
+    }
+}
 #else
 static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
                     flag aIsLargerSignificand)
@@ -296,7 +311,7 @@ static float32 propagateFloat32NaN( float32 a, float32 b STATUS_PARAM)
 *----------------------------------------------------------------------------*/
 #if defined(TARGET_SPARC)
 #define float64_default_nan make_float64(LIT64( 0x7FFFFFFFFFFFFFFF ))
-#elif defined(TARGET_POWERPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA)
+#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA)
 #define float64_default_nan make_float64(LIT64( 0x7FF8000000000000 ))
 #elif SNAN_BIT_IS_ONE
 #define float64_default_nan make_float64(LIT64( 0x7FF7FFFFFFFFFFFF ))
-- 
1.7.2.3

Re: [Qemu-devel] [PATCH v2 8/8] target-ppc: Implement correct NaN propagation rules

[Peter Maydell]

On 4 January 2011 15:15, Aurelien Jarno <aurelien@aurel32.net> wrote:
> Implement the correct NaN propagation rules for ARM targets by
> providing an appropriate pickNaN function.

I think you mean "PPC targets" :-)

-- PMM

Re: [Qemu-devel] [PATCH v2 8/8] target-ppc: Implement correct NaN propagation rules

[Aurelien Jarno]

Peter Maydell a écrit :
> On 4 January 2011 15:15, Aurelien Jarno <aurelien@aurel32.net> wrote:
>> Implement the correct NaN propagation rules for ARM targets by
>> providing an appropriate pickNaN function.
> 
> I think you mean "PPC targets" :-)

Yes, cut and paste...

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

Re: [Qemu-devel] (no subject)

[Peter Maydell]

On 4 January 2011 15:15, Aurelien Jarno <aurelien@aurel32.net> wrote:
> This patch series start by a cleanup to remove dead HPPA code and fix a
> few inconsistencies. The following patch implement implement correct
> NaN propagation rules for MIPS and PowerPC, following commit 3
> 54f211b1a49a7387929e22d6e63849fcba48f8a.

I haven't given a Reviewed-by: for the MIPS and PPC patches in
this series (4,7,8) since I don't know either arch well enough to say
whether the behaviour is right, but they look OK.

-- PMM

Re: [Qemu-devel] (no subject)

[Aurelien Jarno]

On Tue, Jan 04, 2011 at 04:06:13PM +0000, Peter Maydell wrote:
> On 4 January 2011 15:15, Aurelien Jarno <aurelien@aurel32.net> wrote:
> > This patch series start by a cleanup to remove dead HPPA code and fix a
> > few inconsistencies. The following patch implement implement correct
> > NaN propagation rules for MIPS and PowerPC, following commit 3
> > 54f211b1a49a7387929e22d6e63849fcba48f8a.
> 
> I haven't given a Reviewed-by: for the MIPS and PPC patches in
> this series (4,7,8) since I don't know either arch well enough to say
> whether the behaviour is right, but they look OK.
> 

Ok, thanks for the review.

-- 
Aurelien Jarno	                        GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net