From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=49105 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PavjK-0001oN-ME for qemu-devel@nongnu.org; Thu, 06 Jan 2011 14:43:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Paven-0003Tu-Bo for qemu-devel@nongnu.org; Thu, 06 Jan 2011 14:38:01 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:19304) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Paven-0003TQ-3w for qemu-devel@nongnu.org; Thu, 06 Jan 2011 14:37:57 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.69) (envelope-from ) id 1Pavel-0005NT-3U for qemu-devel@nongnu.org; Thu, 06 Jan 2011 19:37:55 +0000 From: Peter Maydell Date: Thu, 6 Jan 2011 19:37:55 +0000 Message-Id: <1294342675-20643-4-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1294342675-20643-1-git-send-email-peter.maydell@linaro.org> References: <1294342675-20643-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH v2 3/3] ARM: wire up the softfloat flush_input_to_zero flag List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Wire up the new softfloat support for flushing input denormals to zero on ARM. The FPSCR FZ bit enables flush-to-zero for both inputs and outputs, but the reporting of when inputs are flushed to zero is via a separate IDC bit rather than the UFC (underflow) bit used when output denormals are flushed to zero. Signed-off-by: Peter Maydell --- target-arm/helper.c | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 05684a2..705b99f 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2242,6 +2242,8 @@ static inline int vfp_exceptbits_from_host(int host_bits) target_bits |= 8; if (host_bits & float_flag_inexact) target_bits |= 0x10; + if (host_bits & float_flag_input_denormal) + target_bits |= 0x80; return target_bits; } @@ -2278,6 +2280,8 @@ static inline int vfp_exceptbits_to_host(int target_bits) host_bits |= float_flag_underflow; if (target_bits & 0x10) host_bits |= float_flag_inexact; + if (target_bits & 0x80) + host_bits |= float_flag_input_denormal; return host_bits; } @@ -2310,8 +2314,10 @@ void HELPER(vfp_set_fpscr)(CPUState *env, uint32_t val) } set_float_rounding_mode(i, &env->vfp.fp_status); } - if (changed & (1 << 24)) + if (changed & (1 << 24)) { set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); + set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); + } if (changed & (1 << 25)) set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status); -- 1.6.3.3