From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=60548 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PbDts-0001MX-8g for qemu-devel@nongnu.org; Fri, 07 Jan 2011 10:06:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PbDtr-0003kl-3R for qemu-devel@nongnu.org; Fri, 07 Jan 2011 10:06:44 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:44803) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PbDtq-0003jc-QI for qemu-devel@nongnu.org; Fri, 07 Jan 2011 10:06:43 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.69) (envelope-from ) id 1PbDti-0006ex-H0 for qemu-devel@nongnu.org; Fri, 07 Jan 2011 15:06:34 +0000 From: Peter Maydell Date: Fri, 7 Jan 2011 15:06:29 +0000 Message-Id: <1294412794-25573-3-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1294412794-25573-1-git-send-email-peter.maydell@linaro.org> References: <1294412794-25573-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 2/7] target-arm: Translate with VFP-enabled from TB flags, not CPUState List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org When translating code, whether the VFP unit is enabled for this TB is stored in a bit in the TB flags. Use this rather than incorrectly reading the FPEXC from the CPUState passed to translation. Signed-off-by: Peter Maydell --- target-arm/translate.c | 14 +++++--------- 1 files changed, 5 insertions(+), 9 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index c391398..d10b484 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -59,6 +59,7 @@ typedef struct DisasContext { #if !defined(CONFIG_USER_ONLY) int user; #endif + int vfp_enabled; } DisasContext; #if defined(CONFIG_USER_ONLY) @@ -2603,12 +2604,6 @@ static void gen_vfp_msr(TCGv tmp) dead_tmp(tmp); } -static inline int -vfp_enabled(CPUState * env) -{ - return ((env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) != 0); -} - static void gen_neon_dup_u8(TCGv var, int shift) { TCGv tmp = new_tmp(); @@ -2653,7 +2648,7 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn) if (!arm_feature(env, ARM_FEATURE_VFP)) return 1; - if (!vfp_enabled(env)) { + if (!s->vfp_enabled) { /* VFP disabled. Only allow fmxr/fmrx to/from some control regs. */ if ((insn & 0x0fe00fff) != 0x0ee00a10) return 1; @@ -3804,7 +3799,7 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn) TCGv tmp2; TCGv_i64 tmp64; - if (!vfp_enabled(env)) + if (!s->vfp_enabled) return 1; VFP_DREG_D(rd, insn); rn = (insn >> 16) & 0xf; @@ -4199,7 +4194,7 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) TCGv tmp, tmp2, tmp3, tmp4, tmp5; TCGv_i64 tmp64; - if (!vfp_enabled(env)) + if (!s->vfp_enabled) return 1; q = (insn & (1 << 6)) != 0; u = (insn >> 24) & 1; @@ -9087,6 +9082,7 @@ static inline void gen_intermediate_code_internal(CPUState *env, dc->user = (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR; } #endif + dc->vfp_enabled = ((tb->flags & (1 << 7)) != 0); cpu_F0s = tcg_temp_new_i32(); cpu_F1s = tcg_temp_new_i32(); cpu_F0d = tcg_temp_new_i64(); -- 1.6.3.3