From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=60523 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PbDtr-0001MS-8o for qemu-devel@nongnu.org; Fri, 07 Jan 2011 10:06:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PbDtp-0003k5-Tq for qemu-devel@nongnu.org; Fri, 07 Jan 2011 10:06:43 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:44803) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PbDtp-0003jc-NF for qemu-devel@nongnu.org; Fri, 07 Jan 2011 10:06:41 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.69) (envelope-from ) id 1PbDti-0006f5-JD for qemu-devel@nongnu.org; Fri, 07 Jan 2011 15:06:34 +0000 From: Peter Maydell Date: Fri, 7 Jan 2011 15:06:33 +0000 Message-Id: <1294412794-25573-7-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1294412794-25573-1-git-send-email-peter.maydell@linaro.org> References: <1294412794-25573-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 6/7] target-arm: Set privileged bit in TB flags correctly for M profile List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org M profile ARM cores don't have a CPSR mode field. Set the bit in the TB flags that indicates non-user mode correctly for these cores. Signed-off-by: Peter Maydell --- target-arm/cpu.h | 17 ++++++++++++++++- 1 files changed, 16 insertions(+), 1 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 340933e..3a2d141 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -443,12 +443,27 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, target_ulong *cs_base, int *flags) { + int privmode; *pc = env->regs[15]; *cs_base = 0; + /* flags word usage: + * [0] thumbstate + * [3..1] vec_len + * [5..4] vec_stride + * [6] privileged (ie not user) mode + * [7] VFP enable bit + * [15..8] condexec bits + */ *flags = env->thumb | (env->vfp.vec_len << 1) | (env->vfp.vec_stride << 4) | (env->condexec_bits << 8); - if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) + if (arm_feature(env, ARM_FEATURE_M)) { + privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1)); + } else { + privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR; + } + if (privmode) { *flags |= (1 << 6); + } if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) *flags |= (1 << 7); } -- 1.6.3.3