From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=48735 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PcQu5-0003rL-N8 for qemu-devel@nongnu.org; Mon, 10 Jan 2011 18:11:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PcQu2-0006Jp-MG for qemu-devel@nongnu.org; Mon, 10 Jan 2011 18:11:57 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:49595) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PcQu2-0006J0-EC for qemu-devel@nongnu.org; Mon, 10 Jan 2011 18:11:54 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.69) (envelope-from ) id 1PcQu0-0003fT-3v for qemu-devel@nongnu.org; Mon, 10 Jan 2011 23:11:52 +0000 From: Peter Maydell Date: Mon, 10 Jan 2011 23:11:51 +0000 Message-Id: <1294701112-14071-4-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1294701112-14071-1-git-send-email-peter.maydell@linaro.org> References: <1294701112-14071-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 3/4] linux-user: ARM: clear the IT bits when invoking a signal handler List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org When invoking a signal handler for an ARM target, make sure the IT bits in the CPSR are cleared. (This would otherwise cause incorrect execution if the IT state was non-zero when an exception occured. This bug has been masked previously because we weren't getting the IT state bits at exception entry right anyway.) Also use the proper cpsr_read()/cpsr_write() interface to update the CPSR rather than manipulating CPUState fields directly. Signed-off-by: Peter Maydell --- linux-user/signal.c | 16 +++++++++------- 1 files changed, 9 insertions(+), 7 deletions(-) diff --git a/linux-user/signal.c b/linux-user/signal.c index c846b8c..0664770 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -1256,6 +1256,14 @@ setup_return(CPUState *env, struct target_sigaction *ka, abi_ulong handler = ka->_sa_handler; abi_ulong retcode; int thumb = handler & 1; + uint32_t cpsr = cpsr_read(env); + + cpsr &= ~CPSR_IT; + if (thumb) { + cpsr |= CPSR_T; + } else { + cpsr &= ~CPSR_T; + } if (ka->sa_flags & TARGET_SA_RESTORER) { retcode = ka->sa_restorer; @@ -1278,13 +1286,7 @@ setup_return(CPUState *env, struct target_sigaction *ka, env->regs[13] = frame_addr; env->regs[14] = retcode; env->regs[15] = handler & (thumb ? ~1 : ~3); - env->thumb = thumb; - -#if 0 -#ifdef TARGET_CONFIG_CPU_32 - env->cpsr = cpsr; -#endif -#endif + cpsr_write(env, cpsr, 0xffffffff); return 0; } -- 1.7.1