From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=47369 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PcUqC-0006yF-Hz for qemu-devel@nongnu.org; Mon, 10 Jan 2011 22:24:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PcUqA-0005XY-Jo for qemu-devel@nongnu.org; Mon, 10 Jan 2011 22:24:12 -0500 Received: from a.mail.sonic.net ([64.142.16.245]:48600) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PcUqA-0005X0-7o for qemu-devel@nongnu.org; Mon, 10 Jan 2011 22:24:10 -0500 From: Richard Henderson Date: Mon, 10 Jan 2011 19:23:48 -0800 Message-Id: <1294716228-9299-8-git-send-email-rth@twiddle.net> In-Reply-To: <1294716228-9299-1-git-send-email-rth@twiddle.net> References: <1294716228-9299-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 7/7] target-ppc: Use deposit operation. List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: agraf@suse.de, aurelien@aurel32.net Use this in implementing rl[wd]imi, at least for the cases that don't require true rotation. Signed-off-by: Richard Henderson --- target-ppc/translate.c | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 74e06d7..f45c0ec 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -1516,6 +1516,11 @@ static void gen_rlwimi(DisasContext *ctx) sh = SH(ctx->opcode); if (likely(sh == 0 && mb == 0 && me == 31)) { tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); + } else if ((31 - me) == sh && mb <= me) { + /* This is a well-behaved bitfield deposit. */ + tcg_gen_deposit_tl (cpu_gpr[rA(ctx->opcode)], + cpu_gpr[rA(ctx->opcode)], + cpu_gpr[rS(ctx->opcode)], sh, me - mb + 1); } else { target_ulong mask; TCGv t1; @@ -1761,6 +1766,11 @@ static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn) me = 63 - sh; if (unlikely(sh == 0 && mb == 0)) { tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); + } else if (mb <= me) { + /* This is a well-behaved bitfield deposit. */ + tcg_gen_deposit_tl (cpu_gpr[rA(ctx->opcode)], + cpu_gpr[rA(ctx->opcode)], + cpu_gpr[rS(ctx->opcode)], sh, me - mb + 1); } else { TCGv t0, t1; target_ulong mask; -- 1.7.2.3