From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=37318 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PcmSF-0008Id-K2 for qemu-devel@nongnu.org; Tue, 11 Jan 2011 17:12:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PcmS5-0003oQ-Qa for qemu-devel@nongnu.org; Tue, 11 Jan 2011 17:12:39 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:5366) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PcmS5-0003mW-Ih for qemu-devel@nongnu.org; Tue, 11 Jan 2011 17:12:29 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.69) (envelope-from ) id 1PcmRu-00057D-DB for qemu-devel@nongnu.org; Tue, 11 Jan 2011 22:12:18 +0000 From: Peter Maydell Date: Tue, 11 Jan 2011 22:12:16 +0000 Message-Id: <1294783938-19629-7-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1294783938-19629-1-git-send-email-peter.maydell@linaro.org> References: <1294783938-19629-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 6/8] target-arm: Translate with condexec bits from TB flags, not CPUState List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org When translating, the condexec bits for the TB are in the TB flags; the CPUState condexec bits may be different. This patch fixes https://bugs.launchpad.net/bugs/604872 where we might segfault if we took an exception in the middle of a TB with an IT block, because when we came to retranslate in cpu_restore_state() the CPUState condexec bits would have advanced compared to the start of the TB and we would generate different (wrong) code. Signed-off-by: Peter Maydell --- target-arm/translate.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index bda5d47..4fe202d 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -9075,8 +9075,8 @@ static inline void gen_intermediate_code_internal(CPUState *env, dc->singlestep_enabled = env->singlestep_enabled; dc->condjmp = 0; dc->thumb = ARM_TBFLAG_THUMB(tb->flags); - dc->condexec_mask = (env->condexec_bits & 0xf) << 1; - dc->condexec_cond = env->condexec_bits >> 4; + dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1; + dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4; #if !defined(CONFIG_USER_ONLY) if (IS_M(env)) { dc->user = ((env->v7m.exception == 0) && (env->v7m.control & 1)); @@ -9105,7 +9105,7 @@ static inline void gen_intermediate_code_internal(CPUState *env, gen_icount_start(); /* Reset the conditional execution bits immediately. This avoids complications trying to do it at the end of the block. */ - if (env->condexec_bits) + if (dc->condexec_mask || dc->condexec_cond) { TCGv tmp = new_tmp(); tcg_gen_movi_i32(tmp, 0); -- 1.6.3.3