From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=37293 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PcmSB-0008He-S5 for qemu-devel@nongnu.org; Tue, 11 Jan 2011 17:12:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PcmS4-0003nt-4y for qemu-devel@nongnu.org; Tue, 11 Jan 2011 17:12:35 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:5366) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PcmS3-0003mW-Uo for qemu-devel@nongnu.org; Tue, 11 Jan 2011 17:12:28 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.69) (envelope-from ) id 1PcmRu-00057F-Dr for qemu-devel@nongnu.org; Tue, 11 Jan 2011 22:12:18 +0000 From: Peter Maydell Date: Tue, 11 Jan 2011 22:12:17 +0000 Message-Id: <1294783938-19629-8-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1294783938-19629-1-git-send-email-peter.maydell@linaro.org> References: <1294783938-19629-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 7/8] target-arm: Set privileged bit in TB flags correctly for M profile List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org M profile ARM cores don't have a CPSR mode field. Set the bit in the TB flags that indicates non-user mode correctly for these cores. Signed-off-by: Peter Maydell --- target-arm/cpu.h | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 3adb118..3cd69c4 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -472,13 +472,19 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, target_ulong *cs_base, int *flags) { + int privmode; *pc = env->regs[15]; *cs_base = 0; *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT) | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT); - if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { + if (arm_feature(env, ARM_FEATURE_M)) { + privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1)); + } else { + privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR; + } + if (privmode) { *flags |= ARM_TBFLAG_PRIV_MASK; } if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { -- 1.6.3.3