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From: <christophe.lyon@st.com>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH 7/8] implement vsli.64, vsri.64
Date: Fri, 28 Jan 2011 16:51:05 +0100	[thread overview]
Message-ID: <1296229866-32011-8-git-send-email-christophe.lyon@st.com> (raw)
In-Reply-To: <1296229866-32011-1-git-send-email-christophe.lyon@st.com>

From: Christophe Lyon <christophe.lyon@st.com>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Christophe Lyon <christophe.lyon@st.com>
---
 target-arm/translate.c |   11 ++++++++++-
 1 files changed, 10 insertions(+), 1 deletions(-)

diff --git a/target-arm/translate.c b/target-arm/translate.c
index 3b14b8f..984df08 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -4711,7 +4711,16 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
                             tcg_gen_add_i64(cpu_V0, cpu_V0, cpu_V1);
                         } else if (op == 4 || (op == 5 && u)) {
                             /* Insert */
-                            cpu_abort(env, "VS[LR]I.64 not implemented");
+                            neon_load_reg64(cpu_V1, rd + pass);
+                            uint64_t mask;
+                            if (op == 4) {
+                                mask = 0xffffffffffffffffull >> -shift;
+                            } else {
+                                mask = 0xffffffffffffffffull << shift;
+                            }
+                            tcg_gen_andi_i64(cpu_V0, cpu_V0, mask);
+                            tcg_gen_andi_i64(cpu_V1, cpu_V1, ~mask);
+                            tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
                         }
                         neon_store_reg64(cpu_V0, rd + pass);
                     } else { /* size < 3 */
-- 
1.7.2.3

  parent reply	other threads:[~2011-01-28 15:51 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-01-28 15:50 [Qemu-devel] [PATCH 0/8] target-arm: Fix Neon instructions VQMOVUN VQRSHL VQRSHRN VQRSHRUN VQSHRN VQSHRUN VSLI VSRI christophe.lyon
2011-01-28 15:50 ` [Qemu-devel] [PATCH 1/8] target-arm: Fixes for several shift instructions: VRSHL, VRSHR, VRSHRN, VSHLL, VRSRA christophe.lyon
2011-01-31  8:20   ` Aurelien Jarno
2011-01-31  9:35     ` Christophe Lyon
2011-01-31  9:44       ` Aurelien Jarno
2011-01-31  9:54         ` Alon Levy
2011-01-31 14:27         ` Christophe Lyon
2011-01-31 15:59           ` Aurelien Jarno
2011-01-31 16:46             ` Peter Maydell
2011-01-31 18:09               ` Christophe Lyon
2011-01-28 15:51 ` [Qemu-devel] [PATCH 2/8] target-arm: Create and use neon_unarrow_sat* helpers christophe.lyon
2011-01-28 15:51 ` [Qemu-devel] [PATCH 3/8] target-arm: VQRSHRN related changes christophe.lyon
2011-01-28 15:51 ` [Qemu-devel] [PATCH 4/8] target-arm: fiddle decoding of 64 bit shift by imm and narrow christophe.lyon
2011-01-28 15:51 ` [Qemu-devel] [PATCH 5/8] target-arm: fix neon vqrshl instruction christophe.lyon
2011-01-28 15:51 ` [Qemu-devel] [PATCH 6/8] target-arm: Fix Neon VQ(R)SHRN instructions christophe.lyon
2011-01-28 15:51 ` christophe.lyon [this message]
2011-01-28 15:51 ` [Qemu-devel] [PATCH 8/8] target-arm: Fix VQRSHL Neon instructions (signed/unsigned 64 bits and signed 32 bits variants) christophe.lyon
2011-01-28 16:03 ` [Qemu-devel] [PATCH 0/8] target-arm: Fix Neon instructions VQMOVUN VQRSHL VQRSHRN VQRSHRUN VQSHRN VQSHRUN VSLI VSRI Peter Maydell

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