From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=48572 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PjvZC-0006T6-QM for qemu-devel@nongnu.org; Mon, 31 Jan 2011 10:21:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PjvZB-0001cF-KX for qemu-devel@nongnu.org; Mon, 31 Jan 2011 10:21:22 -0500 Received: from mail-bw0-f45.google.com ([209.85.214.45]:62056) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PjvZB-0001bM-DJ for qemu-devel@nongnu.org; Mon, 31 Jan 2011 10:21:21 -0500 Received: by mail-bw0-f45.google.com with SMTP id 16so5607723bwz.4 for ; Mon, 31 Jan 2011 07:21:21 -0800 (PST) From: Dmitry Eremin-Solenikov Date: Mon, 31 Jan 2011 18:20:43 +0300 Message-Id: <1296487250-28254-4-git-send-email-dbaryshkov@gmail.com> In-Reply-To: <1296487250-28254-1-git-send-email-dbaryshkov@gmail.com> References: <1296487250-28254-1-git-send-email-dbaryshkov@gmail.com> Subject: [Qemu-devel] [PATCH 04/11] arm-pic: add one extra interrupt to support EXITTB interrupts List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Some ARM processors (consider PXA2xx, Omap1, etc.) want to be able to send CPU_INTERRUPT_EXITTB to the cpu. Support doing that through common arm_pic. Signed-off-by: Dmitry Eremin-Solenikov --- hw/arm-misc.h | 1 + hw/arm_pic.c | 6 +++++- 2 files changed, 6 insertions(+), 1 deletions(-) diff --git a/hw/arm-misc.h b/hw/arm-misc.h index 010acb4..f2e45ee 100644 --- a/hw/arm-misc.h +++ b/hw/arm-misc.h @@ -14,6 +14,7 @@ /* The CPU is also modeled as an interrupt controller. */ #define ARM_PIC_CPU_IRQ 0 #define ARM_PIC_CPU_FIQ 1 +#define ARM_PIC_CPU_WAKE 2 qemu_irq *arm_pic_init_cpu(CPUState *env); /* armv7m.c */ diff --git a/hw/arm_pic.c b/hw/arm_pic.c index f44568c..bd5ce55 100644 --- a/hw/arm_pic.c +++ b/hw/arm_pic.c @@ -38,6 +38,10 @@ static void arm_pic_cpu_handler(void *opaque, int irq, int level) else cpu_reset_interrupt(env, CPU_INTERRUPT_FIQ); break; + case ARM_PIC_CPU_WAKE: + if (env->halted && level) + cpu_interrupt(env, CPU_INTERRUPT_EXITTB); + break; default: hw_error("arm_pic_cpu_handler: Bad interrput line %d\n", irq); } @@ -45,5 +49,5 @@ static void arm_pic_cpu_handler(void *opaque, int irq, int level) qemu_irq *arm_pic_init_cpu(CPUState *env) { - return qemu_allocate_irqs(arm_pic_cpu_handler, env, 2); + return qemu_allocate_irqs(arm_pic_cpu_handler, env, 3); } -- 1.7.2.3