[Qemu-devel] [PATCH 01/11] .gitignore: ignore vi swap files and ctags files

[Qemu-devel] [PATCH 01/11] .gitignore: ignore vi swap files and ctags files

[Dmitry Eremin-Solenikov]

Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
---
 .gitignore |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/.gitignore b/.gitignore
index 3efb4ec..26703e1 100644
--- a/.gitignore
+++ b/.gitignore
@@ -51,6 +51,8 @@ QMP/qmp-commands.txt
 *.vr
 *.d
 *.o
+*.swp
+*.orig
 .pc
 patches
 pc-bios/bios-pq/status
@@ -60,3 +62,4 @@ pc-bios/optionrom/multiboot.bin
 pc-bios/optionrom/multiboot.raw
 .stgit-*
 cscope.*
+tags
-- 
1.7.2.3

[Qemu-devel] [PATCH 02/11] sysbus: print amount of irqs in dev_print

[Dmitry Eremin-Solenikov]

Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
---
 hw/sysbus.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/hw/sysbus.c b/hw/sysbus.c
index 1583bd8..1928b51 100644
--- a/hw/sysbus.c
+++ b/hw/sysbus.c
@@ -178,6 +178,7 @@ static void sysbus_dev_print(Monitor *mon, DeviceState *dev, int indent)
     SysBusDevice *s = sysbus_from_qdev(dev);
     int i;
 
+    monitor_printf(mon, "%*sirq %d\n", indent, "", s->num_irq);
     for (i = 0; i < s->num_mmio; i++) {
         monitor_printf(mon, "%*smmio " TARGET_FMT_plx "/" TARGET_FMT_plx "\n",
                        indent, "", s->mmio[i].addr, s->mmio[i].size);
-- 
1.7.2.3

[Qemu-devel] [PATCH 03/11] arm: drop unused irq-related part of CPUARMState

[Dmitry Eremin-Solenikov]

These two fields were added as a part of ARMv7 support patch (back in
2007), were never used by any code, so can be dropped.

Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
---
 target-arm/cpu.h |    4 ----
 1 files changed, 0 insertions(+), 4 deletions(-)

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 5bcd53a..83d9982 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -157,10 +157,6 @@ typedef struct CPUARMState {
     /* Internal CPU feature flags.  */
     uint32_t features;
 
-    /* Callback for vectored interrupt controller.  */
-    int (*get_irq_vector)(struct CPUARMState *);
-    void *irq_opaque;
-
     /* VFP coprocessor state.  */
     struct {
         float64 regs[32];
-- 
1.7.2.3

[Qemu-devel] [PATCH 04/11] arm-pic: add one extra interrupt to support EXITTB interrupts

[Dmitry Eremin-Solenikov]

Some ARM processors (consider PXA2xx, Omap1, etc.) want to be able to send
CPU_INTERRUPT_EXITTB to the cpu. Support doing that through common arm_pic.

Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
---
 hw/arm-misc.h |    1 +
 hw/arm_pic.c  |    6 +++++-
 2 files changed, 6 insertions(+), 1 deletions(-)

diff --git a/hw/arm-misc.h b/hw/arm-misc.h
index 010acb4..f2e45ee 100644
--- a/hw/arm-misc.h
+++ b/hw/arm-misc.h
@@ -14,6 +14,7 @@
 /* The CPU is also modeled as an interrupt controller.  */
 #define ARM_PIC_CPU_IRQ 0
 #define ARM_PIC_CPU_FIQ 1
+#define ARM_PIC_CPU_WAKE 2
 qemu_irq *arm_pic_init_cpu(CPUState *env);
 
 /* armv7m.c */
diff --git a/hw/arm_pic.c b/hw/arm_pic.c
index f44568c..bd5ce55 100644
--- a/hw/arm_pic.c
+++ b/hw/arm_pic.c
@@ -38,6 +38,10 @@ static void arm_pic_cpu_handler(void *opaque, int irq, int level)
         else
             cpu_reset_interrupt(env, CPU_INTERRUPT_FIQ);
         break;
+    case ARM_PIC_CPU_WAKE:
+        if (env->halted && level)
+            cpu_interrupt(env, CPU_INTERRUPT_EXITTB);
+	break;
     default:
         hw_error("arm_pic_cpu_handler: Bad interrput line %d\n", irq);
     }
@@ -45,5 +49,5 @@ static void arm_pic_cpu_handler(void *opaque, int irq, int level)
 
 qemu_irq *arm_pic_init_cpu(CPUState *env)
 {
-    return qemu_allocate_irqs(arm_pic_cpu_handler, env, 2);
+    return qemu_allocate_irqs(arm_pic_cpu_handler, env, 3);
 }
-- 
1.7.2.3

[Qemu-devel] [PATCH 05/11] pxa2xx_pic: update to use qdev and arm-pic

[Dmitry Eremin-Solenikov]

pxa2xx_pic duplicated some code from arm-pic. Drop it, replacing with
references to arm-pic. Also use qdev/sysbus framework to handle
pxa2xx-pic.

Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
---
 hw/pxa2xx_pic.c |  125 +++++++++++++++++++++++++++++--------------------------
 1 files changed, 66 insertions(+), 59 deletions(-)

diff --git a/hw/pxa2xx_pic.c b/hw/pxa2xx_pic.c
index a36da23..5b5ce72 100644
--- a/hw/pxa2xx_pic.c
+++ b/hw/pxa2xx_pic.c
@@ -10,6 +10,8 @@
 
 #include "hw.h"
 #include "pxa.h"
+#include "arm-misc.h"
+#include "sysbus.h"
 
 #define ICIP	0x00	/* Interrupt Controller IRQ Pending register */
 #define ICMR	0x04	/* Interrupt Controller Mask register */
@@ -31,7 +33,10 @@
 #define PXA2XX_PIC_SRCS	40
 
 typedef struct {
-    CPUState *cpu_env;
+    SysBusDevice busdev;
+    qemu_irq hard_irq;
+    qemu_irq fiq_irq;
+    qemu_irq wake_irq;
     uint32_t int_enabled[2];
     uint32_t int_pending[2];
     uint32_t is_fiq[2];
@@ -44,25 +49,16 @@ static void pxa2xx_pic_update(void *opaque)
     uint32_t mask[2];
     PXA2xxPICState *s = (PXA2xxPICState *) opaque;
 
-    if (s->cpu_env->halted) {
-        mask[0] = s->int_pending[0] & (s->int_enabled[0] | s->int_idle);
-        mask[1] = s->int_pending[1] & (s->int_enabled[1] | s->int_idle);
-        if (mask[0] || mask[1])
-            cpu_interrupt(s->cpu_env, CPU_INTERRUPT_EXITTB);
-    }
+    mask[0] = s->int_pending[0] & (s->int_enabled[0] | s->int_idle);
+    mask[1] = s->int_pending[1] & (s->int_enabled[1] | s->int_idle);
+    qemu_set_irq(s->wake_irq, mask[0] || mask[1]);
 
     mask[0] = s->int_pending[0] & s->int_enabled[0];
     mask[1] = s->int_pending[1] & s->int_enabled[1];
 
-    if ((mask[0] & s->is_fiq[0]) || (mask[1] & s->is_fiq[1]))
-        cpu_interrupt(s->cpu_env, CPU_INTERRUPT_FIQ);
-    else
-        cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_FIQ);
+    qemu_set_irq(s->fiq_irq, ((mask[0] & s->is_fiq[0]) || (mask[1] & s->is_fiq[1])));
 
-    if ((mask[0] & ~s->is_fiq[0]) || (mask[1] & ~s->is_fiq[1]))
-        cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
-    else
-        cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
+    qemu_set_irq(s->hard_irq, ((mask[0] & ~s->is_fiq[0]) || (mask[1] & ~s->is_fiq[1])));
 }
 
 /* Note: Here level means state of the signal on a pin, not
@@ -241,53 +237,36 @@ static CPUWriteMemoryFunc * const pxa2xx_pic_writefn[] = {
     pxa2xx_pic_mem_write,
 };
 
-static void pxa2xx_pic_save(QEMUFile *f, void *opaque)
-{
-    PXA2xxPICState *s = (PXA2xxPICState *) opaque;
-    int i;
-
-    for (i = 0; i < 2; i ++)
-        qemu_put_be32s(f, &s->int_enabled[i]);
-    for (i = 0; i < 2; i ++)
-        qemu_put_be32s(f, &s->int_pending[i]);
-    for (i = 0; i < 2; i ++)
-        qemu_put_be32s(f, &s->is_fiq[i]);
-    qemu_put_be32s(f, &s->int_idle);
-    for (i = 0; i < PXA2XX_PIC_SRCS; i ++)
-        qemu_put_be32s(f, &s->priority[i]);
-}
-
-static int pxa2xx_pic_load(QEMUFile *f, void *opaque, int version_id)
+static int pxa2xx_pic_post_load(void *opaque, int version_id)
 {
-    PXA2xxPICState *s = (PXA2xxPICState *) opaque;
-    int i;
-
-    for (i = 0; i < 2; i ++)
-        qemu_get_be32s(f, &s->int_enabled[i]);
-    for (i = 0; i < 2; i ++)
-        qemu_get_be32s(f, &s->int_pending[i]);
-    for (i = 0; i < 2; i ++)
-        qemu_get_be32s(f, &s->is_fiq[i]);
-    qemu_get_be32s(f, &s->int_idle);
-    for (i = 0; i < PXA2XX_PIC_SRCS; i ++)
-        qemu_get_be32s(f, &s->priority[i]);
-
     pxa2xx_pic_update(opaque);
     return 0;
 }
 
 qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env)
 {
-    PXA2xxPICState *s;
-    int iomemtype;
     qemu_irq *qi;
+    DeviceState *dev;
 
-    s = (PXA2xxPICState *)
-            qemu_mallocz(sizeof(PXA2xxPICState));
-    if (!s)
-        return NULL;
+    qi = arm_pic_init_cpu(env);
 
-    s->cpu_env = env;
+    dev = sysbus_create_varargs("pxa2xx_pic", base,
+            qi[ARM_PIC_CPU_IRQ],
+            qi[ARM_PIC_CPU_FIQ],
+            qi[ARM_PIC_CPU_WAKE],
+            NULL);
+
+    /* Enable IC coprocessor access.  */
+    cpu_arm_set_cp_io(env, 6, pxa2xx_pic_cp_read, pxa2xx_pic_cp_write, dev);
+
+    /* FIXME */
+    return dev->gpio_in;
+}
+
+static int pxa2xx_pic_initfn(SysBusDevice *dev)
+{
+    PXA2xxPICState *s = FROM_SYSBUS(PXA2xxPICState, dev);
+    int iomemtype;
 
     s->int_pending[0] = 0;
     s->int_pending[1] = 0;
@@ -296,18 +275,46 @@ qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env)
     s->is_fiq[0] = 0;
     s->is_fiq[1] = 0;
 
-    qi = qemu_allocate_irqs(pxa2xx_pic_set_irq, s, PXA2XX_PIC_SRCS);
+    sysbus_init_irq(dev, &s->hard_irq);
+    sysbus_init_irq(dev, &s->fiq_irq);
+    sysbus_init_irq(dev, &s->wake_irq);
+
+    qdev_init_gpio_in(&dev->qdev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS);
 
     /* Enable IC memory-mapped registers access.  */
     iomemtype = cpu_register_io_memory(pxa2xx_pic_readfn,
                     pxa2xx_pic_writefn, s, DEVICE_NATIVE_ENDIAN);
-    cpu_register_physical_memory(base, 0x00100000, iomemtype);
+    sysbus_init_mmio(dev, 0x00100000, iomemtype);
 
-    /* Enable IC coprocessor access.  */
-    cpu_arm_set_cp_io(env, 6, pxa2xx_pic_cp_read, pxa2xx_pic_cp_write, s);
+    return 0;
+}
+
+static VMStateDescription vmstate_pxa2xx_pic_regs = {
+    .name = "pxa2xx_pic",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .minimum_version_id_old = 0,
+    .post_load = pxa2xx_pic_post_load,
+    .fields = (VMStateField []) {
+        VMSTATE_UINT32_ARRAY(int_enabled, PXA2xxPICState, 2),
+        VMSTATE_UINT32_ARRAY(int_pending, PXA2xxPICState, 2),
+        VMSTATE_UINT32_ARRAY(is_fiq, PXA2xxPICState, 2),
+        VMSTATE_UINT32(int_idle, PXA2xxPICState),
+        VMSTATE_UINT32_ARRAY(priority, PXA2xxPICState, PXA2XX_PIC_SRCS),
+        VMSTATE_END_OF_LIST(),
+    },
+};
 
-    register_savevm(NULL, "pxa2xx_pic", 0, 0, pxa2xx_pic_save,
-                    pxa2xx_pic_load, s);
+static SysBusDeviceInfo pxa2xx_pic_info = {
+    .init       = pxa2xx_pic_initfn,
+    .qdev.name  = "pxa2xx_pic",
+    .qdev.desc  = "PXA2xx PIC",
+    .qdev.size  = sizeof(PXA2xxPICState),
+    .qdev.vmsd  = &vmstate_pxa2xx_pic_regs,
+};
 
-    return qi;
+static void pxa2xx_pic_register(void)
+{
+    sysbus_register_withprop(&pxa2xx_pic_info);
 }
+device_init(pxa2xx_pic_register);
-- 
1.7.2.3

[Qemu-devel] [PATCH 06/11] pxa2xx_pic: fully encapsulate pic into DeviceState

[Dmitry Eremin-Solenikov]

Currently pxa2xx_pic exposes it's internal gpio_in array. Replace all
references to the array with calls to qdev_get_gpio_in().

Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
---
 hw/mst_fpga.c     |    7 ++++---
 hw/pxa.h          |   10 +++++-----
 hw/pxa2xx.c       |   53 ++++++++++++++++++++++++++---------------------------
 hw/pxa2xx_gpio.c  |    8 ++++----
 hw/pxa2xx_pic.c   |    5 ++---
 hw/pxa2xx_timer.c |   16 ++++++++--------
 6 files changed, 49 insertions(+), 50 deletions(-)

diff --git a/hw/mst_fpga.c b/hw/mst_fpga.c
index 5252fc5..67b544f 100644
--- a/hw/mst_fpga.c
+++ b/hw/mst_fpga.c
@@ -8,6 +8,7 @@
  * This code is licensed under the GNU GPL v2.
  */
 #include "hw.h"
+#include "qdev.h"
 #include "pxa.h"
 #include "mainstone.h"
 
@@ -28,7 +29,7 @@
 #define MST_PCMCIA1		0xe4
 
 typedef struct mst_irq_state{
-	qemu_irq *parent;
+	qemu_irq parent;
 	qemu_irq *pins;
 
 	uint32_t prev_level;
@@ -72,7 +73,7 @@ mst_fpga_set_irq(void *opaque, int irq, int level)
 
 	if(s->intmskena & (1u << irq)) {
 		s->intsetclr = 1u << irq;
-		qemu_set_irq(s->parent[0], level);
+		qemu_set_irq(s->parent, level);
 	}
 }
 
@@ -225,7 +226,7 @@ qemu_irq *mst_irq_init(PXA2xxState *cpu, uint32_t base, int irq)
 	s = (mst_irq_state  *)
 		qemu_mallocz(sizeof(mst_irq_state));
 
-	s->parent = &cpu->pic[irq];
+	s->parent = qdev_get_gpio_in(cpu->pic, irq);
 
 	/* alloc the external 16 irqs */
 	qi  = qemu_allocate_irqs(mst_fpga_set_irq, s, MST_NUM_IRQS);
diff --git a/hw/pxa.h b/hw/pxa.h
index f73d33b..e9a6f7d 100644
--- a/hw/pxa.h
+++ b/hw/pxa.h
@@ -63,15 +63,15 @@
 # define PXA2XX_INTERNAL_SIZE	0x40000
 
 /* pxa2xx_pic.c */
-qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);
+DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);
 
 /* pxa2xx_timer.c */
-void pxa25x_timer_init(target_phys_addr_t base, qemu_irq *irqs);
-void pxa27x_timer_init(target_phys_addr_t base, qemu_irq *irqs, qemu_irq irq4);
+void pxa25x_timer_init(target_phys_addr_t base, DeviceState *pic);
+void pxa27x_timer_init(target_phys_addr_t base, DeviceState *pic);
 
 /* pxa2xx_gpio.c */
 DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
-                CPUState *env, qemu_irq *pic, int lines);
+                CPUState *env, DeviceState *pic, int lines);
 void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);
 
 /* pxa2xx_dma.c */
@@ -125,7 +125,7 @@ typedef struct PXA2xxFIrState PXA2xxFIrState;
 
 typedef struct {
     CPUState *env;
-    qemu_irq *pic;
+    DeviceState *pic;
     qemu_irq reset;
     PXA2xxDMAState *dma;
     DeviceState *gpio;
diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c
index d966846..89550dd 100644
--- a/hw/pxa2xx.c
+++ b/hw/pxa2xx.c
@@ -888,7 +888,7 @@ static int pxa2xx_ssp_init(SysBusDevice *dev)
 
 static inline void pxa2xx_rtc_int_update(PXA2xxState *s)
 {
-    qemu_set_irq(s->pic[PXA2XX_PIC_RTCALARM], !!(s->rtsr & 0x2553));
+    qemu_set_irq(qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM), !!(s->rtsr & 0x2553));
 }
 
 static void pxa2xx_rtc_hzupdate(PXA2xxState *s)
@@ -2065,10 +2065,9 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
 
     s->pic = pxa2xx_pic_init(0x40d00000, s->env);
 
-    s->dma = pxa27x_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
+    s->dma = pxa27x_dma_init(0x40000000, qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
 
-    pxa27x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0],
-                    s->pic[PXA27X_PIC_OST_4_11]);
+    pxa27x_timer_init(0x40a00000, s->pic);
 
     s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121);
 
@@ -2078,26 +2077,26 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
         exit(1);
     }
     s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv,
-                              s->pic[PXA2XX_PIC_MMC], s->dma);
+                              qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), s->dma);
 
     for (i = 0; pxa270_serial[i].io_base; i ++)
         if (serial_hds[i])
 #ifdef TARGET_WORDS_BIGENDIAN
             serial_mm_init(pxa270_serial[i].io_base, 2,
-                           s->pic[pxa270_serial[i].irqn], 14857000/16,
+                           qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn), 14857000/16,
                            serial_hds[i], 1, 1);
 #else
             serial_mm_init(pxa270_serial[i].io_base, 2,
-                           s->pic[pxa270_serial[i].irqn], 14857000/16,
+                           qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn), 14857000/16,
                            serial_hds[i], 1, 0);
 #endif
         else
             break;
     if (serial_hds[i])
-        s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
+        s->fir = pxa2xx_fir_init(0x40800000, qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
                         s->dma, serial_hds[i]);
 
-    s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD]);
+    s->lcd = pxa2xx_lcdc_init(0x44000000, qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
 
     s->cm_base = 0x41300000;
     s->cm_regs[CCCR >> 2] = 0x02000210;	/* 416.0 MHz */
@@ -2129,13 +2128,13 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
     for (i = 0; pxa27x_ssp[i].io_base; i ++) {
         DeviceState *dev;
         dev = sysbus_create_simple("pxa2xx-ssp", pxa27x_ssp[i].io_base,
-                                   s->pic[pxa27x_ssp[i].irqn]);
+                                   qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn));
         s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
     }
 
     if (usb_enabled) {
         sysbus_create_simple("sysbus-ohci", 0x4c000000,
-                             s->pic[PXA2XX_PIC_USBH1]);
+                             qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
     }
 
     s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
@@ -2149,12 +2148,12 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
     register_savevm(NULL, "pxa2xx_rtc", 0, 0, pxa2xx_rtc_save,
                     pxa2xx_rtc_load, s);
 
-    s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
-    s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);
+    s->i2c[0] = pxa2xx_i2c_init(0x40301600, qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
+    s->i2c[1] = pxa2xx_i2c_init(0x40f00100, qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
 
-    s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
+    s->i2s = pxa2xx_i2s_init(0x40400000, qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), s->dma);
 
-    s->kp = pxa27x_keypad_init(0x41500000, s->pic[PXA2XX_PIC_KEYPAD]);
+    s->kp = pxa27x_keypad_init(0x41500000, qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD));
 
     /* GPIO1 resets the processor */
     /* The handler can be overridden by board-specific code */
@@ -2188,9 +2187,9 @@ PXA2xxState *pxa255_init(unsigned int sdram_size)
 
     s->pic = pxa2xx_pic_init(0x40d00000, s->env);
 
-    s->dma = pxa255_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
+    s->dma = pxa255_dma_init(0x40000000, qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
 
-    pxa25x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0]);
+    pxa25x_timer_init(0x40a00000, s->pic);
 
     s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 85);
 
@@ -2200,27 +2199,27 @@ PXA2xxState *pxa255_init(unsigned int sdram_size)
         exit(1);
     }
     s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv,
-                              s->pic[PXA2XX_PIC_MMC], s->dma);
+                              qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), s->dma);
 
     for (i = 0; pxa255_serial[i].io_base; i ++)
         if (serial_hds[i]) {
 #ifdef TARGET_WORDS_BIGENDIAN
             serial_mm_init(pxa255_serial[i].io_base, 2,
-                           s->pic[pxa255_serial[i].irqn], 14745600/16,
+                           qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn), 14745600/16,
                            serial_hds[i], 1, 1);
 #else
             serial_mm_init(pxa255_serial[i].io_base, 2,
-                           s->pic[pxa255_serial[i].irqn], 14745600/16,
+                           qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn), 14745600/16,
                            serial_hds[i], 1, 0);
 #endif
         } else {
             break;
         }
     if (serial_hds[i])
-        s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
+        s->fir = pxa2xx_fir_init(0x40800000, qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
                         s->dma, serial_hds[i]);
 
-    s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD]);
+    s->lcd = pxa2xx_lcdc_init(0x44000000, qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
 
     s->cm_base = 0x41300000;
     s->cm_regs[CCCR >> 2] = 0x02000210;	/* 416.0 MHz */
@@ -2252,13 +2251,13 @@ PXA2xxState *pxa255_init(unsigned int sdram_size)
     for (i = 0; pxa255_ssp[i].io_base; i ++) {
         DeviceState *dev;
         dev = sysbus_create_simple("pxa2xx-ssp", pxa255_ssp[i].io_base,
-                                   s->pic[pxa255_ssp[i].irqn]);
+                                   qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn));
         s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
     }
 
     if (usb_enabled) {
         sysbus_create_simple("sysbus-ohci", 0x4c000000,
-                             s->pic[PXA2XX_PIC_USBH1]);
+                             qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
     }
 
     s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
@@ -2272,10 +2271,10 @@ PXA2xxState *pxa255_init(unsigned int sdram_size)
     register_savevm(NULL, "pxa2xx_rtc", 0, 0, pxa2xx_rtc_save,
                     pxa2xx_rtc_load, s);
 
-    s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
-    s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);
+    s->i2c[0] = pxa2xx_i2c_init(0x40301600, qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
+    s->i2c[1] = pxa2xx_i2c_init(0x40f00100, qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
 
-    s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
+    s->i2s = pxa2xx_i2s_init(0x40400000, qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), s->dma);
 
     /* GPIO1 resets the processor */
     /* The handler can be overridden by board-specific code */
diff --git a/hw/pxa2xx_gpio.c b/hw/pxa2xx_gpio.c
index 789965d..565e8cc 100644
--- a/hw/pxa2xx_gpio.c
+++ b/hw/pxa2xx_gpio.c
@@ -253,7 +253,7 @@ static CPUWriteMemoryFunc * const pxa2xx_gpio_writefn[] = {
 };
 
 DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
-                CPUState *env, qemu_irq *pic, int lines)
+                CPUState *env, DeviceState *pic, int lines)
 {
     DeviceState *dev;
 
@@ -263,9 +263,9 @@ DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
     qdev_init_nofail(dev);
 
     sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
-    sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[PXA2XX_PIC_GPIO_0]);
-    sysbus_connect_irq(sysbus_from_qdev(dev), 1, pic[PXA2XX_PIC_GPIO_1]);
-    sysbus_connect_irq(sysbus_from_qdev(dev), 2, pic[PXA2XX_PIC_GPIO_X]);
+    sysbus_connect_irq(sysbus_from_qdev(dev), 0, qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0));
+    sysbus_connect_irq(sysbus_from_qdev(dev), 1, qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1));
+    sysbus_connect_irq(sysbus_from_qdev(dev), 2, qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X));
 
     return dev;
 }
diff --git a/hw/pxa2xx_pic.c b/hw/pxa2xx_pic.c
index 5b5ce72..7610035 100644
--- a/hw/pxa2xx_pic.c
+++ b/hw/pxa2xx_pic.c
@@ -243,7 +243,7 @@ static int pxa2xx_pic_post_load(void *opaque, int version_id)
     return 0;
 }
 
-qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env)
+DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env)
 {
     qemu_irq *qi;
     DeviceState *dev;
@@ -259,8 +259,7 @@ qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env)
     /* Enable IC coprocessor access.  */
     cpu_arm_set_cp_io(env, 6, pxa2xx_pic_cp_read, pxa2xx_pic_cp_write, dev);
 
-    /* FIXME */
-    return dev->gpio_in;
+    return dev;
 }
 
 static int pxa2xx_pic_initfn(SysBusDevice *dev)
diff --git a/hw/pxa2xx_timer.c b/hw/pxa2xx_timer.c
index b556d11..7ab2cc3 100644
--- a/hw/pxa2xx_timer.c
+++ b/hw/pxa2xx_timer.c
@@ -10,6 +10,7 @@
 #include "hw.h"
 #include "qemu-timer.h"
 #include "sysemu.h"
+#include "qdev.h"
 #include "pxa.h"
 
 #define OSMR0	0x00
@@ -428,7 +429,7 @@ static int pxa2xx_timer_load(QEMUFile *f, void *opaque, int version_id)
 }
 
 static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base,
-                qemu_irq *irqs)
+                DeviceState *pic)
 {
     int i;
     int iomemtype;
@@ -443,7 +444,7 @@ static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base,
 
     for (i = 0; i < 4; i ++) {
         s->timer[i].value = 0;
-        s->timer[i].irq = irqs[i];
+        s->timer[i].irq = qdev_get_gpio_in(pic, PXA2XX_PIC_OST_0 + i);
         s->timer[i].info = s;
         s->timer[i].num = i;
         s->timer[i].level = 0;
@@ -461,24 +462,23 @@ static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base,
     return s;
 }
 
-void pxa25x_timer_init(target_phys_addr_t base, qemu_irq *irqs)
+void pxa25x_timer_init(target_phys_addr_t base, DeviceState *pic)
 {
-    pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs);
+    pxa2xx_timer_info *s = pxa2xx_timer_init(base, pic);
     s->freq = PXA25X_FREQ;
     s->tm4 = NULL;
 }
 
-void pxa27x_timer_init(target_phys_addr_t base,
-                qemu_irq *irqs, qemu_irq irq4)
+void pxa27x_timer_init(target_phys_addr_t base, DeviceState *pic)
 {
-    pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs);
+    pxa2xx_timer_info *s = pxa2xx_timer_init(base, pic);
     int i;
     s->freq = PXA27X_FREQ;
     s->tm4 = (PXA2xxTimer4 *) qemu_mallocz(8 *
                     sizeof(PXA2xxTimer4));
     for (i = 0; i < 8; i ++) {
         s->tm4[i].tm.value = 0;
-        s->tm4[i].tm.irq = irq4;
+        s->tm4[i].tm.irq = qdev_get_gpio_in(pic, PXA27X_PIC_OST_4_11);
         s->tm4[i].tm.info = s;
         s->tm4[i].tm.num = i + 4;
         s->tm4[i].tm.level = 0;
-- 
1.7.2.3

[Qemu-devel] [PATCH 07/11] tc6393xb: correct NAND isr assertion

[Dmitry Eremin-Solenikov]

Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
---
 hw/tc6393xb.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/hw/tc6393xb.c b/hw/tc6393xb.c
index c3fbe4e..0cadcde 100644
--- a/hw/tc6393xb.c
+++ b/hw/tc6393xb.c
@@ -381,7 +381,7 @@ static void tc6393xb_nand_writeb(TC6393xbState *s, target_phys_addr_t addr, uint
         case NAND_DATA + 2:
         case NAND_DATA + 3:
             nand_setio(s->flash, value);
-            s->nand.isr &= 1;
+            s->nand.isr |= 1;
             tc6393xb_nand_irq(s);
             return;
         case NAND_MODE:
-- 
1.7.2.3

[Qemu-devel] [PATCH 08/11] Add scoop post_load callback that sets IRQs to loaded levels

[Dmitry Eremin-Solenikov]

Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
---
 hw/zaurus.c |   19 ++++++++++++++++++-
 1 files changed, 18 insertions(+), 1 deletions(-)

diff --git a/hw/zaurus.c b/hw/zaurus.c
index fca11a5..90fedc9 100644
--- a/hw/zaurus.c
+++ b/hw/zaurus.c
@@ -181,17 +181,34 @@ static int scoop_init(SysBusDevice *dev)
     return 0;
 }
 
+static int scoop_post_load(void *opaque, int version_id)
+{
+    ScoopInfo *s = (ScoopInfo *) opaque;
+    int i;
+    uint32_t level;
+
+    level = s->gpio_level & s->gpio_dir;
+
+    for (i = 1; i < 1 << 16; i <<= 1) {
+        qemu_set_irq(s->handler[i], level & i);
+    }
+
+    s->prev_level = level;
+
+    return 0;
+}
+
 static bool is_version_0 (void *opaque, int version_id)
 {
     return version_id == 0;
 }
 
-
 static const VMStateDescription vmstate_scoop_regs = {
     .name = "scoop",
     .version_id = 1,
     .minimum_version_id = 0,
     .minimum_version_id_old = 0,
+    .post_load = scoop_post_load,
     .fields = (VMStateField []) {
         VMSTATE_UINT16(status, ScoopInfo),
         VMSTATE_UINT16(power, ScoopInfo),
-- 
1.7.2.3

[Qemu-devel] [PATCH 09/11] Drop unnecessary inclusions of pxa.h header

[Dmitry Eremin-Solenikov]

Seceral files contained onnecessary dependencies on hw/pxa.h header.
Drop unused references.

Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
---
 hw/mainstone.c |    2 +-
 hw/mainstone.h |    2 +-
 hw/mst_fpga.c  |    9 ++++-----
 hw/tc6393xb.c  |    1 -
 hw/zaurus.c    |    1 -
 5 files changed, 6 insertions(+), 9 deletions(-)

diff --git a/hw/mainstone.c b/hw/mainstone.c
index 58e3f86..61cac8a 100644
--- a/hw/mainstone.c
+++ b/hw/mainstone.c
@@ -117,7 +117,7 @@ static void mainstone_common_init(ram_addr_t ram_size,
         }
     }
 
-    mst_irq = mst_irq_init(cpu, MST_FPGA_PHYS, PXA2XX_PIC_GPIO_0);
+    mst_irq = mst_irq_init(MST_FPGA_PHYS, qdev_get_gpio_in(cpu->pic, PXA2XX_PIC_GPIO_0));
 
     /* setup keypad */
     printf("map addr %p\n", &map);
diff --git a/hw/mainstone.h b/hw/mainstone.h
index 9618c06..35329f1 100644
--- a/hw/mainstone.h
+++ b/hw/mainstone.h
@@ -33,6 +33,6 @@
 #define S1_IRQ        15
 
 extern qemu_irq
-*mst_irq_init(PXA2xxState *cpu, uint32_t base, int irq);
+*mst_irq_init(uint32_t base, qemu_irq irq);
 
 #endif /* __MAINSTONE_H__ */
diff --git a/hw/mst_fpga.c b/hw/mst_fpga.c
index 67b544f..3a49c84 100644
--- a/hw/mst_fpga.c
+++ b/hw/mst_fpga.c
@@ -9,7 +9,6 @@
  */
 #include "hw.h"
 #include "qdev.h"
-#include "pxa.h"
 #include "mainstone.h"
 
 /* Mainstone FPGA for extern irqs */
@@ -110,7 +109,7 @@ mst_fpga_readb(void *opaque, target_phys_addr_t addr)
 		return s->pcmcia1;
 	default:
 		printf("Mainstone - mst_fpga_readb: Bad register offset "
-			REG_FMT " \n", addr);
+			"0x" TARGET_FMT_plx " \n", addr);
 	}
 	return 0;
 }
@@ -161,7 +160,7 @@ mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
 		break;
 	default:
 		printf("Mainstone - mst_fpga_writeb: Bad register offset "
-			REG_FMT " \n", addr);
+			"0x" TARGET_FMT_plx " \n", addr);
 	}
 }
 
@@ -217,7 +216,7 @@ mst_fpga_load(QEMUFile *f, void *opaque, int version_id)
 	return 0;
 }
 
-qemu_irq *mst_irq_init(PXA2xxState *cpu, uint32_t base, int irq)
+qemu_irq *mst_irq_init(uint32_t base, qemu_irq irq)
 {
 	mst_irq_state *s;
 	int iomemtype;
@@ -226,7 +225,7 @@ qemu_irq *mst_irq_init(PXA2xxState *cpu, uint32_t base, int irq)
 	s = (mst_irq_state  *)
 		qemu_mallocz(sizeof(mst_irq_state));
 
-	s->parent = qdev_get_gpio_in(cpu->pic, irq);
+	s->parent = irq;
 
 	/* alloc the external 16 irqs */
 	qi  = qemu_allocate_irqs(mst_fpga_set_irq, s, MST_NUM_IRQS);
diff --git a/hw/tc6393xb.c b/hw/tc6393xb.c
index 0cadcde..ed49e94 100644
--- a/hw/tc6393xb.c
+++ b/hw/tc6393xb.c
@@ -8,7 +8,6 @@
  * This code is licensed under the GNU GPL v2.
  */
 #include "hw.h"
-#include "pxa.h"
 #include "devices.h"
 #include "flash.h"
 #include "console.h"
diff --git a/hw/zaurus.c b/hw/zaurus.c
index 90fedc9..5d65793 100644
--- a/hw/zaurus.c
+++ b/hw/zaurus.c
@@ -16,7 +16,6 @@
  * with this program; if not, see <http://www.gnu.org/licenses/>.
  */
 #include "hw.h"
-#include "pxa.h"
 #include "sharpsl.h"
 #include "sysbus.h"
 
-- 
1.7.2.3

[Qemu-devel] [PATCH 10/11] mainstone: convert FPGA emulation code to use QDev/SysBus

[Dmitry Eremin-Solenikov]

Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
---
 hw/mainstone.c |   10 +++--
 hw/mainstone.h |    3 --
 hw/mst_fpga.c  |  103 +++++++++++++++++++++++++------------------------------
 3 files changed, 53 insertions(+), 63 deletions(-)

diff --git a/hw/mainstone.c b/hw/mainstone.c
index 61cac8a..7d13972 100644
--- a/hw/mainstone.c
+++ b/hw/mainstone.c
@@ -18,6 +18,7 @@
 #include "sysemu.h"
 #include "flash.h"
 #include "blockdev.h"
+#include "sysbus.h"
 
 static struct keymap map[0xE0] = {
     [0 ... 0xDF] = { -1, -1 },
@@ -77,7 +78,7 @@ static void mainstone_common_init(ram_addr_t ram_size,
     uint32_t sector_len = 256 * 1024;
     target_phys_addr_t mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
     PXA2xxState *cpu;
-    qemu_irq *mst_irq;
+    DeviceState *mst_irq;
     DriveInfo *dinfo;
     int i;
     int be;
@@ -117,16 +118,17 @@ static void mainstone_common_init(ram_addr_t ram_size,
         }
     }
 
-    mst_irq = mst_irq_init(MST_FPGA_PHYS, qdev_get_gpio_in(cpu->pic, PXA2XX_PIC_GPIO_0));
+    mst_irq = sysbus_create_simple("mainstone-fpga", MST_FPGA_PHYS,
+                    qdev_get_gpio_in(cpu->pic, PXA2XX_PIC_GPIO_0));
 
     /* setup keypad */
     printf("map addr %p\n", &map);
     pxa27x_register_keypad(cpu->kp, map, 0xe0);
 
     /* MMC/SD host */
-    pxa2xx_mmci_handlers(cpu->mmc, NULL, mst_irq[MMC_IRQ]);
+    pxa2xx_mmci_handlers(cpu->mmc, NULL, qdev_get_gpio_in(mst_irq, MMC_IRQ));
 
-    smc91c111_init(&nd_table[0], MST_ETH_PHYS, mst_irq[ETHERNET_IRQ]);
+    smc91c111_init(&nd_table[0], MST_ETH_PHYS, qdev_get_gpio_in(mst_irq, ETHERNET_IRQ));
 
     mainstone_binfo.kernel_filename = kernel_filename;
     mainstone_binfo.kernel_cmdline = kernel_cmdline;
diff --git a/hw/mainstone.h b/hw/mainstone.h
index 35329f1..e6a2b67 100644
--- a/hw/mainstone.h
+++ b/hw/mainstone.h
@@ -32,7 +32,4 @@
 #define S1_STSCHG_IRQ 14
 #define S1_IRQ        15
 
-extern qemu_irq
-*mst_irq_init(uint32_t base, qemu_irq irq);
-
 #endif /* __MAINSTONE_H__ */
diff --git a/hw/mst_fpga.c b/hw/mst_fpga.c
index 3a49c84..847053f 100644
--- a/hw/mst_fpga.c
+++ b/hw/mst_fpga.c
@@ -8,8 +8,7 @@
  * This code is licensed under the GNU GPL v2.
  */
 #include "hw.h"
-#include "qdev.h"
-#include "mainstone.h"
+#include "sysbus.h"
 
 /* Mainstone FPGA for extern irqs */
 #define FPGA_GPIO_PIN	0
@@ -28,8 +27,9 @@
 #define MST_PCMCIA1		0xe4
 
 typedef struct mst_irq_state{
+	SysBusDevice busdev;
+
 	qemu_irq parent;
-	qemu_irq *pins;
 
 	uint32_t prev_level;
 	uint32_t leddat1;
@@ -55,7 +55,7 @@ mst_fpga_update_gpio(mst_irq_state *s)
 
 	for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
 		bit = ffs(diff) - 1;
-		qemu_set_irq(s->pins[bit], (level >> bit) & 1 );
+		qemu_set_irq(qdev_get_gpio_in(&s->busdev.qdev, bit), (level >> bit) & 1 );
 	}
 	s->prev_level = level;
 }
@@ -175,66 +175,57 @@ static CPUWriteMemoryFunc * const mst_fpga_writefn[] = {
 	mst_fpga_writeb,
 };
 
-static void
-mst_fpga_save(QEMUFile *f, void *opaque)
-{
-	struct mst_irq_state *s = (mst_irq_state *) opaque;
-
-	qemu_put_be32s(f, &s->prev_level);
-	qemu_put_be32s(f, &s->leddat1);
-	qemu_put_be32s(f, &s->leddat2);
-	qemu_put_be32s(f, &s->ledctrl);
-	qemu_put_be32s(f, &s->gpswr);
-	qemu_put_be32s(f, &s->mscwr1);
-	qemu_put_be32s(f, &s->mscwr2);
-	qemu_put_be32s(f, &s->mscwr3);
-	qemu_put_be32s(f, &s->mscrd);
-	qemu_put_be32s(f, &s->intmskena);
-	qemu_put_be32s(f, &s->intsetclr);
-	qemu_put_be32s(f, &s->pcmcia0);
-	qemu_put_be32s(f, &s->pcmcia1);
-}
-
-static int
-mst_fpga_load(QEMUFile *f, void *opaque, int version_id)
-{
-	mst_irq_state *s = (mst_irq_state *) opaque;
-
-	qemu_get_be32s(f, &s->prev_level);
-	qemu_get_be32s(f, &s->leddat1);
-	qemu_get_be32s(f, &s->leddat2);
-	qemu_get_be32s(f, &s->ledctrl);
-	qemu_get_be32s(f, &s->gpswr);
-	qemu_get_be32s(f, &s->mscwr1);
-	qemu_get_be32s(f, &s->mscwr2);
-	qemu_get_be32s(f, &s->mscwr3);
-	qemu_get_be32s(f, &s->mscrd);
-	qemu_get_be32s(f, &s->intmskena);
-	qemu_get_be32s(f, &s->intsetclr);
-	qemu_get_be32s(f, &s->pcmcia0);
-	qemu_get_be32s(f, &s->pcmcia1);
-	return 0;
-}
-
-qemu_irq *mst_irq_init(uint32_t base, qemu_irq irq)
+static int mst_fpga_init(SysBusDevice *dev)
 {
 	mst_irq_state *s;
 	int iomemtype;
-	qemu_irq *qi;
 
-	s = (mst_irq_state  *)
-		qemu_mallocz(sizeof(mst_irq_state));
+	s = FROM_SYSBUS(mst_irq_state, dev);
 
-	s->parent = irq;
+	sysbus_init_irq(dev, &s->parent);
 
 	/* alloc the external 16 irqs */
-	qi  = qemu_allocate_irqs(mst_fpga_set_irq, s, MST_NUM_IRQS);
-	s->pins = qi;
+	qdev_init_gpio_in(&dev->qdev, mst_fpga_set_irq, MST_NUM_IRQS);
 
 	iomemtype = cpu_register_io_memory(mst_fpga_readfn,
 		mst_fpga_writefn, s, DEVICE_NATIVE_ENDIAN);
-	cpu_register_physical_memory(base, 0x00100000, iomemtype);
-	register_savevm(NULL, "mainstone_fpga", 0, 0, mst_fpga_save,
-                        mst_fpga_load, s);
-	return qi;
+	sysbus_init_mmio(dev, 0x00100000, iomemtype);
+	return 0;
+}
+
+static VMStateDescription vmstate_mst_fpga_regs = {
+	.name = "mainstone_fpga",
+	.version_id = 0,
+	.minimum_version_id = 0,
+	.minimum_version_id_old = 0,
+	.fields = (VMStateField []) {
+		VMSTATE_UINT32(prev_level, mst_irq_state),
+		VMSTATE_UINT32(leddat1, mst_irq_state),
+		VMSTATE_UINT32(leddat2, mst_irq_state),
+		VMSTATE_UINT32(ledctrl, mst_irq_state),
+		VMSTATE_UINT32(gpswr, mst_irq_state),
+		VMSTATE_UINT32(mscwr1, mst_irq_state),
+		VMSTATE_UINT32(mscwr2, mst_irq_state),
+		VMSTATE_UINT32(mscwr3, mst_irq_state),
+		VMSTATE_UINT32(mscrd, mst_irq_state),
+		VMSTATE_UINT32(intmskena, mst_irq_state),
+		VMSTATE_UINT32(intsetclr, mst_irq_state),
+		VMSTATE_UINT32(pcmcia0, mst_irq_state),
+		VMSTATE_UINT32(pcmcia1, mst_irq_state),
+		VMSTATE_END_OF_LIST(),
+	},
+};
+
+static SysBusDeviceInfo mst_fpga_info = {
+	.init = mst_fpga_init,
+	.qdev.name = "mainstone-fpga",
+	.qdev.desc = "Mainstone II FPGA",
+	.qdev.size = sizeof(mst_irq_state),
+	.qdev.vmsd = &vmstate_mst_fpga_regs,
+};
+
+static void mst_fpga_register(void)
+{
+	sysbus_register_withprop(&mst_fpga_info);
 }
+device_init(mst_fpga_register);
-- 
1.7.2.3

[Qemu-devel] [PATCH 11/11] Merge mainstone.h header into mainstone.c

[Dmitry Eremin-Solenikov]

Now the only user of mainstone.h is mainstone.c file. Merge header
into board file.

Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
---
 hw/mainstone.c |   23 ++++++++++++++++++++++-
 hw/mainstone.h |   35 -----------------------------------
 2 files changed, 22 insertions(+), 36 deletions(-)
 delete mode 100644 hw/mainstone.h

diff --git a/hw/mainstone.c b/hw/mainstone.c
index 7d13972..6d10ecb 100644
--- a/hw/mainstone.c
+++ b/hw/mainstone.c
@@ -14,12 +14,33 @@
 #include "net.h"
 #include "devices.h"
 #include "boards.h"
-#include "mainstone.h"
 #include "sysemu.h"
 #include "flash.h"
 #include "blockdev.h"
 #include "sysbus.h"
 
+/* Device addresses */
+#define MST_FPGA_PHYS	0x08000000
+#define MST_ETH_PHYS	0x10000300
+#define MST_FLASH_0		0x00000000
+#define MST_FLASH_1		0x04000000
+
+/* IRQ definitions */
+#define MMC_IRQ       0
+#define USIM_IRQ      1
+#define USBC_IRQ      2
+#define ETHERNET_IRQ  3
+#define AC97_IRQ      4
+#define PEN_IRQ       5
+#define MSINS_IRQ     6
+#define EXBRD_IRQ     7
+#define S0_CD_IRQ     9
+#define S0_STSCHG_IRQ 10
+#define S0_IRQ        11
+#define S1_CD_IRQ     13
+#define S1_STSCHG_IRQ 14
+#define S1_IRQ        15
+
 static struct keymap map[0xE0] = {
     [0 ... 0xDF] = { -1, -1 },
     [0x1e] = {0,0}, /* a */
diff --git a/hw/mainstone.h b/hw/mainstone.h
deleted file mode 100644
index e6a2b67..0000000
--- a/hw/mainstone.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * PXA270-based Intel Mainstone platforms.
- *
- * Copyright (c) 2007 by Armin Kuster <akuster@kama-aina.net> or
- *                                    <akuster@mvista.com>
- *
- * This code is licensed under the GNU GPL v2.
- */
-
-#ifndef __MAINSTONE_H__
-#define __MAINSTONE_H__
-
-/* Device addresses */
-#define MST_FPGA_PHYS	0x08000000
-#define MST_ETH_PHYS	0x10000300
-#define MST_FLASH_0		0x00000000
-#define MST_FLASH_1		0x04000000
-
-/* IRQ definitions */
-#define MMC_IRQ       0
-#define USIM_IRQ      1
-#define USBC_IRQ      2
-#define ETHERNET_IRQ  3
-#define AC97_IRQ      4
-#define PEN_IRQ       5
-#define MSINS_IRQ     6
-#define EXBRD_IRQ     7
-#define S0_CD_IRQ     9
-#define S0_STSCHG_IRQ 10
-#define S0_IRQ        11
-#define S1_CD_IRQ     13
-#define S1_STSCHG_IRQ 14
-#define S1_IRQ        15
-
-#endif /* __MAINSTONE_H__ */
-- 
1.7.2.3

Re: [Qemu-devel] [PATCH 03/11] arm: drop unused irq-related part of CPUARMState

[Peter Maydell]

On 31 January 2011 15:20, Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> wrote:
> These two fields were added as a part of ARMv7 support patch (back in
> 2007), were never used by any code, so can be dropped.
>
> Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

-- PMM

[Qemu-devel] Re: [PATCH 01/11] .gitignore: ignore vi swap files and ctags files

[Dmitry Eremin-Solenikov]

Hi,

What about these patches?

-- 
With best wishes
Dmitry

Re: [Qemu-devel] [PATCH 08/11] Add scoop post_load callback that sets IRQs to loaded levels

[andrzej zaborowski]

Hi Dmitry,

On 31 January 2011 16:20, Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> wrote:
> Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
> ---
>  hw/zaurus.c |   19 ++++++++++++++++++-
>  1 files changed, 18 insertions(+), 1 deletions(-)
>
> diff --git a/hw/zaurus.c b/hw/zaurus.c
> index fca11a5..90fedc9 100644
> --- a/hw/zaurus.c
> +++ b/hw/zaurus.c
> @@ -181,17 +181,34 @@ static int scoop_init(SysBusDevice *dev)
>     return 0;
>  }
>
> +static int scoop_post_load(void *opaque, int version_id)
> +{
> +    ScoopInfo *s = (ScoopInfo *) opaque;
> +    int i;
> +    uint32_t level;
> +
> +    level = s->gpio_level & s->gpio_dir;
> +
> +    for (i = 1; i < 1 << 16; i <<= 1) {
> +        qemu_set_irq(s->handler[i], level & i);

This looks like it's going to try to set s->handler[1] up to
s->handler[32k] (should be 0 to 15), otherwise this patch is a good
catch.

Cheers

Re: [Qemu-devel] [PATCH 05/11] pxa2xx_pic: update to use qdev and arm-pic

[andrzej zaborowski]

On 31 January 2011 16:20, Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> wrote:
> pxa2xx_pic duplicated some code from arm-pic. Drop it, replacing with
> references to arm-pic. Also use qdev/sysbus framework to handle
> pxa2xx-pic.

The duplication involves about 4 lines of code, at this level I
strongly prefer to not add a level of calls that can't be inlined in a
fast path.  I guess the choice not to involve arm_pic was conscious.

Otherwise this patch and all the remaining patches look good to me,
except some minor remarks:

In patch 6 I'd prefer not to call qdev_get_gpio_in in
pxa2xx_rtc_int_update and similarly in patch 10 in
mst_fpga_update_gpio, let's store the irq's in the state struct.

I also prefer not to make lines shorter than 80 chars longer, they
wrap on my netbook.

I pushed patches 1-3.

Cheers

Re: [Qemu-devel] [PATCH 05/11] pxa2xx_pic: update to use qdev and arm-pic

[Dmitry Eremin-Solenikov]

On 2/11/11, andrzej zaborowski <balrogg@gmail.com> wrote:
> On 31 January 2011 16:20, Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
> wrote:
>> pxa2xx_pic duplicated some code from arm-pic. Drop it, replacing with
>> references to arm-pic. Also use qdev/sysbus framework to handle
>> pxa2xx-pic.
>
> The duplication involves about 4 lines of code, at this level I
> strongly prefer to not add a level of calls that can't be inlined in a
> fast path.  I guess the choice not to involve arm_pic was conscious.

I just planned to later reuse allocated arm-pic IRQ's (the new one) to
be passed to pxa2xx-gpio (to drop usage of cpu-env). I think. I can
still allocate
arm-pic but use only the last IRQ from it. Will that be suitable for you?

>
> Otherwise this patch and all the remaining patches look good to me,
> except some minor remarks:
>
> In patch 6 I'd prefer not to call qdev_get_gpio_in in
> pxa2xx_rtc_int_update and similarly in patch 10 in

Fixed.

> mst_fpga_update_gpio, let's store the irq's in the state struct.

Will inlining qdev_get_gpio_in with direct access to qdev->gpio_in[] OK?

>
> I also prefer not to make lines shorter than 80 chars longer, they
> wrap on my netbook.
>
> I pushed patches 1-3.
>
> Cheers
>


-- 
With best wishes
Dmitry

Re: [Qemu-devel] [PATCH 05/11] pxa2xx_pic: update to use qdev and arm-pic

[Dmitry Eremin-Solenikov]

Hello,

On 2/11/11, Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> wrote:
> On 2/11/11, andrzej zaborowski <balrogg@gmail.com> wrote:
>> On 31 January 2011 16:20, Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
>> wrote:
>>> pxa2xx_pic duplicated some code from arm-pic. Drop it, replacing with
>>> references to arm-pic. Also use qdev/sysbus framework to handle
>>> pxa2xx-pic.
>>
>> The duplication involves about 4 lines of code, at this level I
>> strongly prefer to not add a level of calls that can't be inlined in a
>> fast path.  I guess the choice not to involve arm_pic was conscious.
>
> I just planned to later reuse allocated arm-pic IRQ's (the new one) to
> be passed to pxa2xx-gpio (to drop usage of cpu-env). I think. I can
> still allocate
> arm-pic but use only the last IRQ from it. Will that be suitable for you?

I recollected the reason for this change: there is no clean way to pass CPUState
to qdev. So It's either DEFINE_PROP_PTR() - like hack, or
encapsulating thins into
qemu_irq

arm_pic is used by several other ARM SoC emulators.

-- 
With best wishes
Dmitry

Re: [Qemu-devel] [PATCH 05/11] pxa2xx_pic: update to use qdev and arm-pic

[andrzej zaborowski]

Hi,

On 11 February 2011 21:24, Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> wrote:
> On 2/11/11, Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> wrote:
>> I just planned to later reuse allocated arm-pic IRQ's (the new one) to
>> be passed to pxa2xx-gpio (to drop usage of cpu-env). I think. I can
>> still allocate
>> arm-pic but use only the last IRQ from it. Will that be suitable for you?
>
> I recollected the reason for this change: there is no clean way to pass CPUState
> to qdev. So It's either DEFINE_PROP_PTR() - like hack, or
> encapsulating thins into
> qemu_irq

That's true, but in that patchset pxa2xx_pic is not turned into a qdev
device (separate from pxa2xx core).  Do you think there's any value in
doing that?  I think it's ok if it doesn't present any
issues/overheads or if there's a clear benefit from doing that.

Cheers

Re: [Qemu-devel] [PATCH 05/11] pxa2xx_pic: update to use qdev and arm-pic

[andrzej zaborowski]

On 11 February 2011 21:18, Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> wrote:
> On 2/11/11, andrzej zaborowski <balrogg@gmail.com> wrote:
>> On 31 January 2011 16:20, Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
>> wrote:
>>> pxa2xx_pic duplicated some code from arm-pic. Drop it, replacing with
>>> references to arm-pic. Also use qdev/sysbus framework to handle
>>> pxa2xx-pic.
>>
>> The duplication involves about 4 lines of code, at this level I
>> strongly prefer to not add a level of calls that can't be inlined in a
>> fast path.  I guess the choice not to involve arm_pic was conscious.
>
> I just planned to later reuse allocated arm-pic IRQ's (the new one) to
> be passed to pxa2xx-gpio (to drop usage of cpu-env). I think. I can
> still allocate
> arm-pic but use only the last IRQ from it. Will that be suitable for you?
>
>>
>> Otherwise this patch and all the remaining patches look good to me,
>> except some minor remarks:
>>
>> In patch 6 I'd prefer not to call qdev_get_gpio_in in
>> pxa2xx_rtc_int_update and similarly in patch 10 in
>
> Fixed.
>
>> mst_fpga_update_gpio, let's store the irq's in the state struct.
>
> Will inlining qdev_get_gpio_in with direct access to qdev->gpio_in[] OK?

There's a comment in hw/qdev.h that says not to do that.  I'm not sure
why qdev_get_gpio_in is not a static inline function, but it'd be
easiest to store the irq array in the mst_fpga's state.

Cheers

Re: [Qemu-devel] [PATCH 08/11] Add scoop post_load callback that sets IRQs to loaded levels

[Dmitry Eremin-Solenikov]

On 2/11/11, andrzej zaborowski <balrogg@gmail.com> wrote:
> Hi Dmitry,
>
> On 31 January 2011 16:20, Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
> wrote:
>> Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
>> ---
>>  hw/zaurus.c |   19 ++++++++++++++++++-
>>  1 files changed, 18 insertions(+), 1 deletions(-)
>>
>> diff --git a/hw/zaurus.c b/hw/zaurus.c
>> index fca11a5..90fedc9 100644
>> --- a/hw/zaurus.c
>> +++ b/hw/zaurus.c
>> @@ -181,17 +181,34 @@ static int scoop_init(SysBusDevice *dev)
>>     return 0;
>>  }
>>
>> +static int scoop_post_load(void *opaque, int version_id)
>> +{
>> +    ScoopInfo *s = (ScoopInfo *) opaque;
>> +    int i;
>> +    uint32_t level;
>> +
>> +    level = s->gpio_level & s->gpio_dir;
>> +
>> +    for (i = 1; i < 1 << 16; i <<= 1) {
>> +        qemu_set_irq(s->handler[i], level & i);
>
> This looks like it's going to try to set s->handler[1] up to
> s->handler[32k] (should be 0 to 15), otherwise this patch is a good
> catch.

Oops. Fixed in a resent patch.


-- 
With best wishes
Dmitry