From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=44373 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Pl57a-0005S7-Q4 for qemu-devel@nongnu.org; Thu, 03 Feb 2011 14:45:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Pl55Z-0002OG-L5 for qemu-devel@nongnu.org; Thu, 03 Feb 2011 14:43:34 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:26905) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Pl55Z-0002NL-DK for qemu-devel@nongnu.org; Thu, 03 Feb 2011 14:43:33 -0500 From: Peter Maydell Date: Thu, 3 Feb 2011 19:43:21 +0000 Message-Id: <1296762205-3043-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 0/4] target-arm: Fix decoding of preload and hint insns List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: patches@linaro.org The primary aim of this patch series is to fix the decoding of the preload and hint instruction space (PLD, PLDW, PLI). Some of these instructions (PLDW and some unallocated space which should NOP) are v7MP only, so we introduce a feature flag for cores with the v7MP extensions. The flag also lets us clean up the MPIDR coprocessor register implementation so it isn't A9 specific any more. Tested as usual with random instruction sequences. Peter Maydell (4): target-arm: Add CPU feature flag for v7MP target-arm: Clean up handling of MPIDR target-arm: Fix decoding of preload and memory hint space target-arm: Fix decoding of Thumb preload and hint space target-arm/cpu.h | 3 +- target-arm/helper.c | 32 +++++++++++++-- target-arm/translate.c | 98 +++++++++++++++++++++++++++++++++++------------ 3 files changed, 102 insertions(+), 31 deletions(-)