qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: qemu@gibson.dropbear.id.au
To: qemu-devel@nongnu.org
Cc: paulus@samba.org, agraf@suse.de, anton@samba.org
Subject: [Qemu-devel] [PATCH 26/28] Add a PAPR TCE-bypass mechanism for the pSeries machine
Date: Tue, 15 Feb 2011 15:56:37 +1100	[thread overview]
Message-ID: <1297745799-26148-27-git-send-email-qemu@gibson.dropbear.id.au> (raw)
In-Reply-To: <1297745799-26148-1-git-send-email-qemu@gibson.dropbear.id.au>

From: David Gibson <david@gibson.dropbear.id.au>

Usually, PAPR virtual IO devices use a virtual IOMMU mechanism, TCEs,
to mediate all DMA transfers.  While this is necessary for some sorts of
operation, it can be complex to program and slow for others.

This patch implements a mechanism for bypassing TCE translation, treating
"IO" addresses as plain (guest) physical memory addresses.  This has two
main uses:
 * Simple, but 64-bit aware programs like firmwares can use the VIO devices
without the complexity of TCE setup.
 * The guest OS can optionally use the TCE bypass to improve performance in
suitable situations.

The mechanism used is a per-device flag which disables TCE translation.
The flag is toggled with some (hypervisor-implemented) RTAS methods.

Signed-off-by: Ben Herrenschmidt <benh@kernel.crashing.org>
---
 hw/spapr_vio.c |   82 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 hw/spapr_vio.h |    5 +++
 2 files changed, 87 insertions(+), 0 deletions(-)

diff --git a/hw/spapr_vio.c b/hw/spapr_vio.c
index 5ea2aa2..df30f85 100644
--- a/hw/spapr_vio.c
+++ b/hw/spapr_vio.c
@@ -224,6 +224,12 @@ int spapr_tce_dma_write(VIOsPAPRDevice *dev, uint64_t taddr, const void *buf,
             (unsigned long long)taddr, size);
 #endif
 
+    /* Check for bypass */
+    if (dev->flags & VIO_PAPR_FLAG_DMA_BYPASS) {
+        cpu_physical_memory_write(taddr, buf, size);
+        return 0;
+    }
+
     while(size) {
         uint64_t tce;
         uint32_t lsize;
@@ -308,6 +314,12 @@ int spapr_tce_dma_read(VIOsPAPRDevice *dev, uint64_t taddr, void *buf,
             (unsigned long long)taddr, size);
 #endif
 
+    /* Check for bypass */
+    if (dev->flags & VIO_PAPR_FLAG_DMA_BYPASS) {
+        cpu_physical_memory_read(taddr, buf, size);
+        return 0;
+    }
+
     while(size) {
         uint64_t tce;
         uint32_t lsize;
@@ -505,6 +517,72 @@ int spapr_vio_send_crq(VIOsPAPRDevice *dev, uint8_t *crq)
     return 0;
 }
 
+/* "quiesce" handling */
+
+static void spapr_vio_quiesce_one(VIOsPAPRDevice *dev)
+{
+    dev->flags &= ~VIO_PAPR_FLAG_DMA_BYPASS;
+    
+    if (dev->rtce_table) {
+        size_t size = (dev->rtce_window_size >> SPAPR_VIO_TCE_PAGE_SHIFT)
+            * sizeof(VIOsPAPR_RTCE);
+        memset(dev->rtce_table, 0, size);
+    }
+
+    dev->crq.qladdr = 0;
+    dev->crq.qsize = 0;
+    dev->crq.qnext = 0;
+}
+
+static void rtas_set_tce_bypass(sPAPREnvironment *spapr, uint32_t token,
+                                uint32_t nargs, target_ulong args,
+                                uint32_t nret, target_ulong rets)
+{
+    VIOsPAPRBus *bus = spapr->vio_bus;
+    VIOsPAPRDevice *dev;
+    uint32_t unit, enable;
+
+    if (nargs != 2) {
+        rtas_st(rets, 0, -3);
+        return;
+    }
+    unit = rtas_ld(args, 0);
+    enable = rtas_ld(args, 1);
+    dev = spapr_vio_find_by_reg(bus, unit);
+    if (!dev) {
+        rtas_st(rets, 0, -3);
+        return;
+    }
+    if (enable) {
+        dev->flags |= VIO_PAPR_FLAG_DMA_BYPASS;
+    } else {
+        dev->flags &= ~VIO_PAPR_FLAG_DMA_BYPASS;
+    }
+
+    rtas_st(rets, 0, 0);
+}
+
+static void rtas_quiesce(sPAPREnvironment *spapr, uint32_t token,
+                         uint32_t nargs, target_ulong args,
+                         uint32_t nret, target_ulong rets)
+{
+    VIOsPAPRBus *bus = spapr->vio_bus;
+    DeviceState *qdev;
+    VIOsPAPRDevice *dev = NULL;
+
+    if (nargs != 0) {
+        rtas_st(rets, 0, -3);
+        return;
+    }
+ 
+    QLIST_FOREACH(qdev, &bus->bus.children, sibling) {
+        dev = (VIOsPAPRDevice *)qdev;
+        spapr_vio_quiesce_one(dev);
+    }
+
+    rtas_st(rets, 0, 0);
+}
+
 static int spapr_vio_busdev_init(DeviceState *dev, DeviceInfo *info)
 {
     VIOsPAPRDeviceInfo *_info = (VIOsPAPRDeviceInfo *)info;
@@ -581,6 +659,10 @@ VIOsPAPRBus *spapr_vio_bus_init(void)
     spapr_register_hypercall(H_SEND_CRQ, h_send_crq);
     spapr_register_hypercall(H_ENABLE_CRQ, h_enable_crq);
 
+    /* RTAS calls */
+    spapr_rtas_register("ibm,set-tce-bypass", rtas_set_tce_bypass);
+    spapr_rtas_register("quiesce", rtas_quiesce);
+
     for (_info = device_info_list; _info; _info = _info->next) {
         VIOsPAPRDeviceInfo *info = (VIOsPAPRDeviceInfo *)_info;
 
diff --git a/hw/spapr_vio.h b/hw/spapr_vio.h
index b7d0daa..841b043 100644
--- a/hw/spapr_vio.h
+++ b/hw/spapr_vio.h
@@ -48,6 +48,8 @@ typedef struct VIOsPAPR_CRQ {
 typedef struct VIOsPAPRDevice {
     DeviceState qdev;
     uint32_t reg;
+    uint32_t flags;
+#define VIO_PAPR_FLAG_DMA_BYPASS        0x1
     qemu_irq qirq;
     uint32_t vio_irq_num;
     target_ulong signal_state;
@@ -104,4 +106,7 @@ void spapr_vlan_create(VIOsPAPRBus *bus, uint32_t reg, NICInfo *nd,
 void spapr_vscsi_create(VIOsPAPRBus *bus, uint32_t reg,
                         qemu_irq qirq, uint32_t vio_irq_num);
 
+int spapr_tce_set_bypass(uint32_t unit, uint32_t enable);
+void spapr_vio_quiesce(void);
+
 #endif /* _HW_SPAPR_VIO_H */
-- 
1.7.1

  parent reply	other threads:[~2011-02-15  4:57 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-02-15  4:56 [Qemu-devel] RFC: Implement emulation of pSeries logical partitions (v2) qemu
2011-02-15  4:56 ` [Qemu-devel] [PATCH 01/28] Add TAGS and *~ to .gitignore qemu
2011-02-15  4:56 ` [Qemu-devel] [PATCH 02/28] Clean up PowerPC SLB handling code qemu
2011-02-15  4:56 ` [Qemu-devel] [PATCH 03/28] Allow qemu_devtree_setprop() to take arbitrary values qemu
2011-02-15  4:56 ` [Qemu-devel] [PATCH 04/28] Add a hook to allow hypercalls to be emulated on PowerPC qemu
2011-02-15  4:56 ` [Qemu-devel] [PATCH 05/28] Implement PowerPC slbmfee and slbmfev instructions qemu
2011-02-15  4:56 ` [Qemu-devel] [PATCH 06/28] Implement missing parts of the logic for the POWER PURR qemu
2011-02-15  4:56 ` [Qemu-devel] [PATCH 07/28] Correct ppc popcntb logic, implement popcntw and popcntd qemu
2011-02-15  4:56 ` [Qemu-devel] [PATCH 08/28] Clean up slb_lookup() function qemu
2011-02-15  4:56 ` [Qemu-devel] [PATCH 09/28] Parse SDR1 on mtspr instead of at translate time qemu
2011-02-15  4:56 ` [Qemu-devel] [PATCH 10/28] Use "hash" more consistently in ppc mmu code qemu
2011-02-15  4:56 ` [Qemu-devel] [PATCH 11/28] Better factor the ppc hash translation path qemu
2011-02-15  4:56 ` [Qemu-devel] [PATCH 12/28] Support 1T segments on ppc qemu
2011-02-15  4:56 ` [Qemu-devel] [PATCH 13/28] Add POWER7 support for ppc qemu
2011-02-15  4:56 ` [Qemu-devel] [PATCH 14/28] Start implementing pSeries logical partition machine qemu
2011-02-15  4:56 ` [Qemu-devel] [PATCH 15/28] Implement the bus structure for PAPR virtual IO qemu
2011-02-15  4:56 ` [Qemu-devel] [PATCH 16/28] Virtual hash page table handling on pSeries machine qemu
2011-02-15  4:56 ` [Qemu-devel] [PATCH 17/28] Implement hcall based RTAS for pSeries machines qemu
2011-02-15  4:56 ` [Qemu-devel] [PATCH 18/28] Implement assorted pSeries hcalls and RTAS methods qemu
2011-02-15  4:56 ` [Qemu-devel] [PATCH 19/28] Implement the PAPR (pSeries) virtualized interrupt controller (xics) qemu
2011-02-15  4:56 ` [Qemu-devel] [PATCH 20/28] Add PAPR H_VIO_SIGNAL hypercall and infrastructure for VIO interrupts qemu
2011-02-15  4:56 ` [Qemu-devel] [PATCH 21/28] Add (virtual)_interrupt to PAPR virtual tty device qemu
2011-02-15  4:56 ` [Qemu-devel] [PATCH 22/28] Implement TCE translation for sPAPR VIO qemu
2011-02-15  4:56 ` [Qemu-devel] [PATCH 23/28] Implement sPAPR Virtual LAN (ibmveth) qemu
2011-02-15  4:56 ` [Qemu-devel] [PATCH 24/28] Implement PAPR CRQ hypercalls qemu
2011-02-15  4:56 ` [Qemu-devel] [PATCH 25/28] Implement PAPR virtual SCSI interface (ibmvscsi) qemu
2011-02-15  4:56 ` qemu [this message]
2011-02-15  4:56 ` [Qemu-devel] [PATCH 27/28] Add SLOF-based partition firmware for pSeries machine, allowing more boot options qemu
2011-02-15  4:56 ` [Qemu-devel] [PATCH 28/28] Implement PAPR VPA functions for pSeries shared processor partitions qemu

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1297745799-26148-27-git-send-email-qemu@gibson.dropbear.id.au \
    --to=qemu@gibson.dropbear.id.au \
    --cc=agraf@suse.de \
    --cc=anton@samba.org \
    --cc=paulus@samba.org \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).