From: Michael Walle <michael@walle.cc>
To: qemu-devel@nongnu.org
Cc: Blue Swirl <blauwirbel@gmail.com>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
Michael Walle <michael@walle.cc>, Alexander Graf <agraf@suse.de>,
Richard Henderson <rth@twiddle.net>
Subject: [Qemu-devel] [PATCH 14/17] lm32: todo and documentation
Date: Thu, 17 Feb 2011 23:45:15 +0100 [thread overview]
Message-ID: <1297982718-21865-15-git-send-email-michael@walle.cc> (raw)
In-Reply-To: <1297982718-21865-1-git-send-email-michael@walle.cc>
This patch adds general target documentation and a todo list.
Signed-off-by: Michael Walle <michael@walle.cc>
---
target-lm32/README | 46 ++++++++++++++++++++++++++++++++++++++++++++++
target-lm32/TODO | 3 +++
2 files changed, 49 insertions(+), 0 deletions(-)
create mode 100644 target-lm32/README
create mode 100644 target-lm32/TODO
diff --git a/target-lm32/README b/target-lm32/README
new file mode 100644
index 0000000..a1c2c7e
--- /dev/null
+++ b/target-lm32/README
@@ -0,0 +1,46 @@
+LatticeMico32 target
+--------------------
+
+General
+-------
+All opcodes including the JUART CSRs are supported.
+
+
+JTAG UART
+---------
+JTAG UART is routed to a serial console device. For the current boards it
+is the second one. Ie to enable it in the qemu virtual console window use
+the following command line parameters:
+ -serial vc -serial vc
+This will make serial0 (the lm32_uart) and serial1 (the JTAG UART)
+available as virtual consoles.
+
+
+Programmatically terminate the emulator
+----------------------------------------
+Originally neither the LatticeMico32 nor its peripherals support a
+mechanism to shut down the machine. Emulation aware programs can write to a
+to a special register within the system control block to shut down the
+virtual machine. For more details see hw/lm32_sys.c. The lm32-evr is the
+first BSP which instantiate this model. A (32 bit) write to 0xfff0000
+causes a vm shutdown.
+
+
+Special instructions
+--------------------
+The translation recognizes one special instruction to halt the cpu:
+ and r0, r0, r0
+On real hardware this instruction is a nop. It is not used by GCC and
+should (hopefully) not be used within hand-crafted assembly.
+Insert this instruction in your idle loop to reduce the cpu load on the
+host.
+
+
+Ignoring the MSB of the address bus
+-----------------------------------
+Some SoC ignores the MSB on the address bus. Thus creating a shadow memory
+area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
+0x80000000-0xffffffff is not cached and used to access IO devices. This
+behaviour can be enabled with:
+ cpu_lm32_set_phys_msb_ignore(env, 1);
+
diff --git a/target-lm32/TODO b/target-lm32/TODO
new file mode 100644
index 0000000..b9ea0c8
--- /dev/null
+++ b/target-lm32/TODO
@@ -0,0 +1,3 @@
+* disassembler (lm32-dis.c)
+* linux-user emulation
+* native bp/wp emulation (?)
--
1.7.2.3
next prev parent reply other threads:[~2011-02-17 22:45 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-02-17 22:45 [Qemu-devel] [PATCH 00/17 v3] LatticeMico32 target Michael Walle
2011-02-17 22:45 ` [Qemu-devel] [PATCH 01/17] LatticeMico32 target support Michael Walle
2011-02-17 22:45 ` [Qemu-devel] [PATCH 02/17] lm32: translation routines Michael Walle
2011-02-17 22:45 ` [Qemu-devel] [PATCH 03/17] lm32: translation code helper Michael Walle
2011-02-17 22:45 ` [Qemu-devel] [PATCH 04/17] lm32: machine state loading/saving Michael Walle
2011-02-17 22:45 ` [Qemu-devel] [PATCH 05/17] lm32: gdbstub support Michael Walle
2011-02-17 22:45 ` [Qemu-devel] [PATCH 06/17] lm32: interrupt controller model Michael Walle
2011-02-17 22:45 ` [Qemu-devel] [PATCH 07/17] lm32: juart model Michael Walle
2011-02-17 22:45 ` [Qemu-devel] [PATCH 08/17] lm32: pic and juart helper functions Michael Walle
2011-02-17 22:45 ` [Qemu-devel] [PATCH 09/17] lm32: timer model Michael Walle
2011-02-17 22:45 ` [Qemu-devel] [PATCH 10/17] lm32: uart model Michael Walle
2011-02-17 22:45 ` [Qemu-devel] [PATCH 11/17] lm32: system control model Michael Walle
2011-02-17 22:45 ` [Qemu-devel] [PATCH 12/17] lm32: support for creating device tree Michael Walle
2011-02-17 22:45 ` [Qemu-devel] [PATCH 13/17] lm32: EVR32 and uclinux BSP Michael Walle
2011-02-17 22:45 ` Michael Walle [this message]
2011-02-17 22:45 ` [Qemu-devel] [PATCH 15/17] lm32: opcode testsuite Michael Walle
2011-02-17 22:45 ` [Qemu-devel] [PATCH 16/17] Add lm32 target to configure Michael Walle
2011-02-17 22:45 ` [Qemu-devel] [PATCH 17/17] MAINTAINERS: add LatticeMico32 maintainer Michael Walle
2011-02-24 23:03 ` [Qemu-devel] [PATCH 00/17 v3] LatticeMico32 target Michael Walle
2011-03-01 21:31 ` Edgar E. Iglesias
2011-03-05 9:55 ` Blue Swirl
2011-03-06 22:47 ` Michael Walle
2011-03-07 13:20 ` Edgar E. Iglesias
2011-03-13 22:36 ` Michael Walle
-- strict thread matches above, loose matches on Subject: below --
2011-02-10 23:11 [Qemu-devel] [PATCH 00/17 v2] " Michael Walle
2011-02-10 23:12 ` [Qemu-devel] [PATCH 14/17] lm32: todo and documentation Michael Walle
2011-02-11 20:41 ` Blue Swirl
2011-02-11 22:45 ` Michael Walle
2011-02-12 8:00 ` Blue Swirl
2011-01-31 0:30 [Qemu-devel] [PATCH 00/17] LatticeMico32 target Michael Walle
2011-01-31 0:30 ` [Qemu-devel] [PATCH 14/17] lm32: todo and documentation Michael Walle
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